ASIC Design Engineer

Responsible for RTL design, simulation, and verification for ASIC/SoC products.Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team.Create reusable internal IPs for AI and/or in-memory computing products.Handle IP integration and validation and support post-Si testing and...

Roles & Responsibilities Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Build reusable testbench, constrained-random/directed test cases, and...

Roles & ResponsibilitiesRESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO:• Develop microarchitecture and RTL design and verification for Expedera AI accelerators• Explore microarchitecture and architecture for design space optimization (power/performance/area)• Collaborate with HW/SW architects in HW specification process, HW/SW co-design• Execute...

Responsibilities:Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...

This will be a permanent position based in Jurong East There are 4 open positions: SoC Architecture Scope of Work Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Work on SoC floorplan with architect and APR; SoC...

Roles & ResponsibilitiesJOB DESCRIPTION· Discussion with system engineers on SoC architecture and feedback on optimization.· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Discussion with synthesis engineer and back-end engineer on design optimization.· SoC DFT...

JOB DESCRIPTIONDiscussion with system engineers on SoC architecture and feedback on optimization.Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;Discussion with synthesis engineer and back-end engineer on design optimization.   SoC DFT support;SoC verification plan and SoC...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

Roles & ResponsibilitiesJOB DESCRIPTION· Work with system engineers on timing requirements and feedback on optimization.· Work on SoC timing constraint, synthesis and timing closure.· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains· Conduct formal verification for release comparison.· Support back-end...

Roles & ResponsibilitiesJOB DESCRIPTION· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support;...

This will be a permanent position based in Jurong East Scope of Work Produce detailed module level and SoC level testplans Create ASIC verification environment (stimulus, checkers, assertions, monitors and scoreboards). Produce directed and constrain-random verification functional tests Run simulation using EDA tools to verify functional spec works as...

Roles & ResponsibilitiesJOB DESCRIPTION· Work with SoC Integration and SoC Timing on power structure optimization· Work on UPF development to support different stages of implementation flow and SoC verification· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains· Conduct power structure check at different...

JOB DESCRIPTIONWork with system engineers on timing requirements and feedback on optimization.  Work on SoC timing constraint, synthesis and timing closure.Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains Conduct formal verification for release comparison.Support back-end implementation on timing violation...

JOB DESCRIPTION Work with system engineers on timing requirements and feedback on optimization.   Work on SoC timing constraint, synthesis and timing closure. Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains  Conduct formal verification for release comparison. Support back-end implementation on timing...

JOB DESCRIPTIONWork with SoC Integration and SoC Timing on power structure optimizationWork on UPF development to support different stages of implementation flow and SoC verificationWork on power structure, eg. Isolation of power domains, level-shifter crossing voltage domainsConduct power structure check at different implementation stages. Support back-end...

JOB DESCRIPTION Work with SoC Integration and SoC Timing on power structure optimization Work on UPF development to support different stages of implementation flow and SoC verification Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains Conduct power structure check at different implementation stages.  Support...

Roles & ResponsibilitiesJOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective...

Roles & ResponsibilitiesJOB DESCRIPTION· Discussion with system engineers on IP requirement and micro architecture.· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.· Support SoC designer on integration, timing constraints and power domain setting.· Support IP verification for verification plan...

Roles & ResponsibilitiesResponsibilities: The Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc . ...

Roles & ResponsibilitiesJOB DESCRIPTIONIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective...