ASIC Physical Design Engineer

Roles & Responsibilities Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or in-memory computing products. Handle IP integration and validation and support post-Si...

Responsible for RTL design, simulation, and verification for ASIC/SoC products.Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team.Create reusable internal IPs for AI and/or in-memory computing products.Handle IP integration and validation and support post-Si testing and...

Roles & Responsibilities Work closely with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. Create and maintain infrastructure/environment for automation verification of SoC architecture, function and performance. Build reusable testbench, constrained-random/directed test cases, and...

Roles & ResponsibilitiesRESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO:• Develop microarchitecture and RTL design and verification for Expedera AI accelerators• Explore microarchitecture and architecture for design space optimization (power/performance/area)• Collaborate with HW/SW architects in HW specification process, HW/SW co-design• Execute...

Roles & ResponsibilitiesJOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure...

Responsibilities:Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

JOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure successful tapeout, active...

This will be a permanent position based in Jurong East There are 4 open positions: SoC Architecture Scope of Work Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Work on SoC floorplan with architect and APR; SoC...

Roles & ResponsibilitiesResponsibilities: Working on IC physical design of 12nm/7nm/6nm/5nm and below advanced process chip, from RTL to GDS. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff. Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block...

Roles & ResponsibilitiesResponsibilities: Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the...

Roles & Responsibilities Responsible for the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape out. Liaise with the front-end design team to complete the chip floorplan, clock architecture, and power plan. Study the...

Roles & ResponsibilitiesJOB DESCRIPTION· Discussion with system engineers on SoC architecture and feedback on optimization.· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Discussion with synthesis engineer and back-end engineer on design optimization.· SoC DFT...

JOB DESCRIPTION. Discussion with system engineers on SoC architecture and feedback on optimization.. Work on SoC integration system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc. Discussion with synthesis engineer and back-end engineer on design optimization.. SoC DFT support. SoC verification plan and SoC...

JOB DESCRIPTIONDiscussion with system engineers on SoC architecture and feedback on optimization.Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;Discussion with synthesis engineer and back-end engineer on design optimization.   SoC DFT support;SoC verification plan and SoC...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

Responsible for the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape out.Liaise with the front-end design team to complete the chip floorplan, clock architecture, and power plan.Study the physical design methodology of...

Responsibilities:Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.Block owner, take block of 23 Million instances, working on Synthesis/APR(auto place and route)/SignoffBlock coordinator role for more than 510 blocks, solving the critical issue and give the solution to block owners.TOP role...

Roles & ResponsibilitiesJOB DESCRIPTION· Work with system engineers on timing requirements and feedback on optimization.· Work on SoC timing constraint, synthesis and timing closure.· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains· Conduct formal verification for release comparison.· Support back-end...

Roles & ResponsibilitiesJOB DESCRIPTION· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support;...