Physical Design Engineer

Roles & ResponsibilitiesJOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure...

JOB DESCRIPTIONTo provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna).In order to ensure successful tapeout, active...

Roles & ResponsibilitiesResponsibilities: Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the...

Roles & Responsibilities Responsible for the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape out. Liaise with the front-end design team to complete the chip floorplan, clock architecture, and power plan. Study the...

Responsible for the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape out.Liaise with the front-end design team to complete the chip floorplan, clock architecture, and power plan.Study the physical design methodology of...

Responsibilities:Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.Block owner, take block of 23 Million instances, working on Synthesis/APR(auto place and route)/SignoffBlock coordinator role for more than 510 blocks, solving the critical issue and give the solution to block owners.TOP role...

Responsibilities:Working on IC physical design of 12nm/7nm/6nm/5nm and below advanced process chip, from RTL to GDS.Block owner, take block of 23 Million instances, working on Synthesis/APR(auto place and route)/Signoff.Block coordinator role for more than 510 blocks, solving the critical issue and give the solution to block owners.Requirements:Basic...

ResponsibilitiesAdvanced low-power physical design/integration flow developmentSynthesis, floor planning and place & routeFull-chip floor planning and layoutPower network design and analysisSupport signoff timing closure, power integrity, and signal integrityPhysical Verification using DRC, LVSQualificationsDegree or related field required3+ years industry...

Roles & ResponsibilitiesJob Description Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies. Work closely with...

Roles & ResponsibilitiesJob Description Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies. Work closely with...

Roles & ResponsibilitiesJob Description Working on 6nm and below advanced process project APR and Timing/PI sign-off Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros) Take the Block or Block coordinator role for complex blocks Do early prediction for critical APR/Timing/PI issuesJob Requirements ...

about the companyMy client is a leading manufacturer of digital electronic products. With an outstanding international reputation in its field and a great emphasis on training & development, it is certainly a great brand to explore if you are seeking for greater achievement in your careerabout the jobDesign and realization of the chip floorplan, clock...

Roles & Responsibilitiesabout the companyMy client is a leading manufacturer of digital electronic products. With an outstanding international reputation in its field and a great emphasis on training & development, it is certainly a great brand to explore if you are seeking for greater achievement in your careerabout the job Design and realization of the...

Job DescriptionWork on RTL to GDS, including synthesis, placement, clock tree insertion and routing.Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.Work closely with other groups like Analog Design,...

Job DescriptionWork on RTL to GDS, including synthesis, placement, clock tree insertion and routing.Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.Work closely with other groups like Analog Design,...

ResponsibilitiesAbout Us Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Helo, and Resso, as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and...

Roles & ResponsibilitiesWe are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions...

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience...

Roles & ResponsibilitiesAvailable Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components ...

This is a hybrid internship role for an Interior Designer, with the expectation of both physical presence in Singapore and flexible remote working from home. The Interior Designer will be responsible for day-to-day tasks such as space planning, creating construction drawings (layout plan, M&E drawing, details drawing and 3D visualizations) , specifying FF&E...