Rtl Design Engineer

Responsibilities:Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness.Integrate and validate IP blocks for seamless system functionality.Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.Collaborate with backend team in RTL coding, implementation, and synthesis for...

Multinational CompanyPermanent RoleCompany ExpansionThe company is top leading developer of integrated circuit to create energy-efficient semiconductor solutions for IoT endpoint devices.ResponsibilitiesDesign, verify and implement modules and/or subsystems used within the SoC designs.Use verilog design language and implement the development with the Cadence...

The company is top leading developer of integrated circuit to create energy efficient semiconductor solutions for IoT endpoint devices.ResponsibilitiesDesign, verify and implement modules and/or subsystems used within the SoC designs.Use verilog design language and implement the development with the Cadence tool suite.Verification development will include...

Multinational CompanyPermanent RoleCompany ExpansionThe company is top leading developer of integrated circuit to create energy-efficient semiconductor solutions for IoT endpoint devices.ResponsibilitiesDesign, verify and implement modules and/or subsystems used within the SoC designs.Use verilog design language and implement the development with the Cadence...

Roles & Responsibilities Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or in-memory computing products. Handle IP integration and validation and support post-Si...

Roles & Responsibilities Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or in-memory computing products. Handle IP integration and validation and support post-Si...

Roles & ResponsibilitiesResponsibilities: Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robustness. Integrate and validate IP blocks for seamless system functionality. Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs. Collaborate with backend team in RTL coding,...

Roles & Responsibilities•MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design•Experience with Verilog and system Verilog•Experience with VCS, Verdi or other industry standard tools•Experience with pre-layout simulation and post-layout simulation•Understanding of the design flow. Ability to work...

Roles & ResponsibilitiesJob Description & Requirements Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level Develop IP level/SoC level test plans based on the design/architectural specs. Coverage Analysis and Coding Run simulations & regressions, debug test failures to identify test case issues & RTL...

Job Description - RTL coding and modulelevel verification of digital IC circuit blocks Assist DV engineering team for systemlevel verification and debug Assist in creating and maintaining design documentation Assist in the completion of signoff GDSII working with DFT and PD engineering teams.Requirement - Highly motivated and driven to solve challenging...

Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or inmemory computing products. Handle IP integration and validation and support postSi testing and...

We are seeking a FPGA/ASIC Engineer to collaborate with our technical team and take charge of designing and implementing high-performance digital circuits on FPGA or ASIC. Your role will involve managing the entire FPGA build flow, including RTL coding, verification, and timing closure.Responsibilities Design and implement highperformance digital circuits on...

Roles & ResponsibilitiesJob Responsibilities· Co-design the module and SoC design specification· Responsible for the module RTL design and SoC integration· Participate in module and SoC verification· Responsible for RTL link check, synthesis and power analysis· Participate in FPGA prototype verificationJob Requirements· EE, Communication, Computes...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

JOB DESCRIPTIONDiscussion with system engineers on SoC architecture and feedback on optimization.Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;Discussion with synthesis engineer and back-end engineer on design optimization.   SoC DFT support;SoC verification plan and SoC...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

Roles & ResponsibilitiesDescriptionAs a digital IC design engineer, the candidate will be working in a dynamic team that develops cut edging automotive Battery Management System and Optical Control IC products. Will be responsible for several aspects in digital IC design area such as micro-architecture, block/chip level design and implementation,...

Roles & ResponsibilitiesPosition Overview: The Staff/Senior Design Engineer will be responsible for developing micro-architecture for Image Signal Processing Unit (ISP) and Computer Vision Unit (CV) related algorithms. They will utilize RTL design using Verilog/System Verilog coding and High-Level Synthesis (HLS) tools like Catapult. Additionally, they will...

Roles & ResponsibilitiesKey Responsibilities: Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.Key Requirements: Master/Degree in Electrical Engineering with 3 years of ASIC design. experience preferred. ...

Roles & ResponsibilitiesKey Responsibilities: Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.Key Requirements: Master/Degree in Electrical Engineering with 5 years of ASIC design. experience preferred. ...