Design Verification Team Lead, Soc
7 days ago
Take charge of verification team.
- Designing & deploy verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
- Perform test plan reviews systematically and execute the plan on-time with high quality.
- Achieve zero-defect with the best and smartest approach to the large verification space.
**Requirements**:
- Bachelor & Master in Electrical Engineering or Computer Engineering
- At least 10 years of relevant experience.
- Expertise in Universal Verification Methodology (UVM) processes.
- Quality-minded, and highly driven for excellence.
- Excellent team player and good communication skills.
- Experience in video processing and video analytics is a plus.
EnviroDynamics Solutions Pte Ltd
Poon Wai Soon, Bernard
Reg. No: R2197713
EA License No.: 12C6285
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