Digital Verification Engineer

Digital Verification Engineer page is loaded## Digital Verification Engineerlocations: Singapore, Kallangtime type: Full timeposted on: Posted Todaytime left to apply: End Date: February 28, 2026 (30+ days left to apply)job requisition id: R Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has...

**About Our Client** Our client is a global semiconductor chip manufacturer with a has a strong presence in Chinese and South East Asia markets. You will be joining a young and energetic team with strong growth opportunities! **Highlights**: - Work alongside global teams (China, Singapore and more) - Young team in Singapore with huge growth potential -...

Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal...

Responsibilities Define verification plans and test cases based on chip design specifications, and establish the verification environment Collaborate with chip design engineers in identifying and fixing design defects and continuously improve verification coverage Participate in gate-level simulation and formal verification Optimize tools and the...

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Position Summary** Perform ASIC Verification **Key Responsibilities** - Digital IC Verification - Develop and maintain verification environment for module and SOC level level using UVM methodology. - Create and...

Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal...

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition.• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.• Develop ASIC verification environment including all the respective components such as...

Overview Thales is a global technology leader trusted by governments, institutions, and enterprises to tackle their most demanding challenges. From quantum applications and artificial intelligence to cybersecurity and 6G innovation, our solutions empower critical decisions rooted in human intelligence. Operating at the forefront of aerospace and space,...

JOB DESCRIPTION: Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts...

Overview Thales is a global technology leader trusted by governments, institutions, and enterprises to tackle their most demanding challenges. From quantum applications and artificial intelligence to cybersecurity and 6G innovation, our solutions empower critical decisions rooted in human intelligence. Operating at the forefront of aerospace and space,...