DFT Engineer

17 hours ago

Singapore Silicon Labs Full time $120,000 - $180,000 per year

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at 

What we're looking for:

Person will be responsible for DFT Architecture including JTAG functionality, boundary scan, hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, implement test logic for analog macros. Person should also be responsible to develop firmware driven cost-effective test strategies methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on ATE. Person should be capable of generate and debug DFT patterns on tester.

Skills you'll need:

  • Expert knowledge of DFT architecture on complex Design with multiple clock domains.

  • Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, Bridging fault and Small delay defects .

  • Experience in industry standard DFT tools - Mentor Tessent suite, Synopsys DFT compiler.

  • Expert knowledge on scan coverage improvement and Test time reduction.

  • Experience with standard JTAG protocol and Boundary scan.

  • Should have participated in successful tapeouts of DSM SoC/ASIC chips at 40nm or below and achieved test targets.

  • Experience working with cross functional global teams

  • Experience in Low-Power DFT requirements.

  • Experience in Low-Power MBIST architectures and Memory testing.

Required Education/Experience: 

3-5 years in Industry

Bachelors/MS in Electrical Engineering, or equivalent

  • Experience of working with Advantest, Teradyne testers.

  • Experience in DFT related RTL integration.

  • Excellent debugging and Scripting skills.

  • Excellent communication and analytical skills

  • Mentoring skills

  • Exceptional problem-solving skills

Benefits & Perks :

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Equity Rewards (RSUs)

  • Employee Stock Purchase Plan (ESPP)

  • Insurance plans with Outpatient cover

  • Flexible work policy

#LI-Hybrid

#LI-DK1

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

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