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Senior/ Verification Engineer
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JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption.Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for talents to join our journey for rapid growth. What will you be working on: 1. Involved into simulation and verification tasks of SOC / IP designs; 2. Working with design teams for design function verification & performance evaluation; 3. Reusable verification environment development, methodology research & flow setup 4. Supporting design debug, FPGA emulation, lab validation, silicon bring up and mass production ,etc What are we looking for: 1. BS/MS in Electronic/communication/automation engineering or related major. 2. Experienced with System Verilog, C/C++, tcl/python/perl. 3. Solid project experience of SOC / IP designs : have taken responsibility for 4. verification of SOC top/sys/ip/bus(CPU,DSP,GPU,DMA,AMBA,PCIE, 5. MIPI, DDR, USB, UFS, etc) 6. Experience with EDA tools : VCS / Verdi / Modelsim or similar tool sets. 7. Experience with verification methodology (UVM,etc). 8. Hands on verification platforM/Flow setup is a plus. 9. Familiar with SOC design flow. 10. Knowledge with low power design verification, familiar with UPF / SDC is a plus. 11. Experience or knowledge with simulation accelerate flow / platform (Palladium/ZEBU). 12. Self Motivated and fast learner.
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