Senior Verification Engineer

Roles & ResponsibilitiesJob Responsibilities: Develop module level and system level verification plans based on design spec; Build verification environment using UVM infrastructure ; Define reasonable functional coverage according to the verification plan, add test vectors, and meet the requirements for functional coverage and code coverage; Complete the...

Roles & ResponsibilitiesJob Responsibilities: Develop module level and system level verification plans based on design spec; Build verification environment using UVM infrastructure ; Define reasonable functional coverage according to the verification plan, add test vectors, and meet the requirements for functional coverage and code coverage; Complete the...

Roles & ResponsibilitiesIn this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT...

JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption.Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for...

- Meet the Team As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips. Responsibilities- Block and IP Verification- Block-level verification to validate block performance and adherence to requirements- Generate...

Job DescriptionWe are seeking a highly skilled Verification Engineer to join our team. As a key member, you will be responsible for developing and reviewing test plans, verification environment/testbench in Module/IP/SOC level, and verification IP and reference model.You will implement test with randomization based coverage driven verification methodology,...

**Design Verification Engineer, Senior**: Responsibilities include: - Actively understand Design under Test (DUT); - Define and peer-review test plan; - Write test patterns as per defined test plan; - Execute test patterns, actively debugging RTL simulation issues; - Execute regression of test patterns; - Collect and actively improve RTL code coverage; -...

Roles & ResponsibilitiesAbout the Job:​Join our client's passionate and dynamic verification team where we constantly push the boundaries of technology. As a Design Verification Engineer, you will be working with cutting-edge verification methodologies to tackle ever-increasing design complexities. You'll be involved in developing and deploying...

Roles & ResponsibilitiesJob Responsibilities: Develop module level and system level verification plans based on design spec; Build verification environment using UVM infrastructure ; Define reasonable functional coverage according to the verification plan, add test vectors, and meet the requirements for functional coverage and code coverage; Complete the...

**Responsibilities**: - Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications - Design and develop verification testbenches using industry-standard verification languages and methodologies - Write and execute test cases to verify mixed-signal circuits for functionality,...

- Meet the Team As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips. **Responsibilities**: - Block and IP Verification- Block-level verification to validate block performance and adherence to requirements-...

Looking for a new challenge? We are hiring a Senior Manager / Director - Chip Verification to lead and manage a team of engineers and project managers. In your new role you will: - **Lead and manage **a team of engineers and project managers - **Partner/collaborate **with project managers and line managers - **On-time project execution **and delivering...

As a **Design Verification Engineer **, you will play a pivotal role in shaping the future of cutting-edge IoT devices. Immerse yourself in a dynamic environment where you will tackle intricate digital and mixed-signal designs, including sophisticated systems-on-chip (SoCs) featuring multiple CPUs, NPU, ISP, audio sub-system, video processing, digital signal...

Digital Verification EngineerWe are seeking an experienced Digital Verification Engineer to join our team at SVENTL ASIA PACIFIC PTE. LTD. As a Digital Verification Engineer, you will be responsible for designing and implementing verification environments and tests for IP level and SoC Level testing.Main Responsibilities:Developing and implementing...

**: We are seeking a **SoC Verification Engineer**to test and validate **System-on-Chip (SoC)**designs. You will work with cross-functional teams to ensure chip functionality through verification using **UVM**, **SystemVerilog**, **Python**, and other cutting-edge tools. **Responsibilities**: - Develop **verification plans**for module and system-level...

**Location** Singapore, Central Singapore **Job Type** Full Time **Salary** $5,000 - $9,000 Per Month **Date Posted** 1 hour ago Additional Details **Job ID** 5273 **Job Views** 1 **Job Description**: Roles & Responsibilities - Experience in UVM verification methodology - Experience in developing and deploying state-of-the-art verification...

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Position Summary** Perform ASIC Verification **Key Responsibilities** - Digital IC Verification - Develop and maintain verification environment for module and SOC level level using UVM methodology. - Create and...

**Job description** - Experience in UVM verification methodology - Experience in developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification - Disciplined, quality-minded, and highly driven for excellence, -...

Design Verification Engineer Our client is a young and ambitious SoC design house who dedicated to wireless area. To expand their R&D team and explore overseas market, they are now looking for various design talents in Singapore. **Responsibilities**: - You will responsible for verification platform setup, compile and certificate automated scripts,...

We are in search of a Senior Manager/Director - Chip Verification to lead and inspire a talented team of engineers. This role will be pivotal in ensuring timely project execution and achieving excellence in SoC verification sign-off, Analog Mixed Signal verification, Functional Safety Verification, and the creation of Functional Test patterns. In your new...