Spot Timing Lead Engineer

**Company Overview**:
**Company Overview**

Ambiq® is bringing intelligence to billions of endpoints. Using the revolutionary Sub-threshold Power Optimized Technology (SPOT) Platform, Ambiq’s record-breaking ultra-low power SoCs free device makers to put intelligence everywhere. Ambiq’s SoCs have enabled more than 100 million battery-powered devices in markets ranging from wearables to hearables to smart credit cards to smart home devices to smart industrial devices. Ambiq develops and sells SoCs and software solutions with innovative and fast-moving teams in the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore.

We are just getting started with these first 100 million devices. Come join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

**Scope**

The **SPOT Timing Lead Engineer **will plan and lead timing related activities for Ambiq’s next-generation technology development. This will include defining signoff criteria, analysis, design methodology development and day-to-day management of tape-outs driven by Ambiq’s Advanced Development team. The lead will work closely with other members of the Advanced Development team and the broader engineering community at Ambiq to develop and deploy Timing signoff related flows and methodologies to support production chip development.

**Specific Responsibilities**
- Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.
- Define and own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area.
- Be responsible for PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions.
- Work with product development teams to rapidly deploy timing related methods in products.
- Plan and lead timing and other related activities for test chips owned by the Advanced Development team. As part of this effort, lead a small group of internal and/or contract resources.
- Maintain a relationship with and collaborate with 3rd party CAD tool vendors and fab during the development of new flows and methodologies. Validate and refine new techniques as part of a team that is building complex test chips in advanced FinFET nodes.

**Education and Experience**:

- A master’s degree in electrical engineering or a related field is required.
- Hands-on experience in STA, Power integrity and EM signoff.
- Familiar with important aspects of timing of SoC designs in bulk and FinFET technologies.
- Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, aging, HTOL, soft errors among others.
- Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
- Experience with large design STA and Timing Closure. Familiar with ECO techniques and implementation.
- Experience in one or more static timing and power integrity tools (e.g., PrimeTime, Tempus, Redhawk, Voltus).
- Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
- Experience with Power integrity and reliability signoff methodologies including EM, Aging, HTOL, TDDB etc
- Experience developing new technologies and transitioning those technologies to production is highly desirable.
- Good programming skills with Perl and TCL.

**Key Personal and Professional Attributes