Spot Low Power Engineer

5 days ago

Central Singapore Ambiq Micro Full time

**Company Overview**:
**Company Overview**

Ambiq® is bringing intelligence to billions of endpoints. Using the revolutionary Sub-threshold Power Optimized Technology (SPOT) Platform, Ambiq’s record-breaking ultra-low power SoCs free device makers to put intelligence everywhere. Ambiq’s SoCs have enabled more than 100 million battery-powered devices in markets ranging from wearables to hearables to smart credit cards to smart home devices to smart industrial devices. Ambiq develops and sells SoCs and software solutions with innovative and fast-moving teams in the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore.

We are just getting started with these first 100 million devices. Come join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.

**Scope**

The **SPOT Low Power Engineer** (SLPE) will drive power related activities for Ambiq’s next-generation products. This will include pre-silicon power modeling, power estimation, post-silicon power correlation and power reduction. The SLPE will work closely with other members of the Advanced Development team and the broader engineering community at Ambiq to develop ultra-low power design methodologies, test them out, and then deploy them in test chips at 12nm and beyond. The SLPE will also work closely with the Engineering team to transition new low power methodologies to support production chip development.

**Specific Responsibilities**
- Work with System, Architecture and Product Planning team to build and own pre-silicon power modeling, power estimation and post-silicon power correlation. Work closely with the Engineering team to track RTL and gate level power changes during project execution and co-ordinate with design engineers and architects to deploy low power design methods for power reduction.
- Investigate, plan, and test sub-threshold and near-threshold design methodologies and other related low power techniques for power optimization (e.g., customized standard cells, level shifters, retention flops, multi-bit flops etc.
- Validate and refine new low power design techniques as part of a team that is building complex test chips in advanced nodes (e.g., 12nm and beyond). Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new methodologies.

**Education and Experience**:

- A master’s degree in electrical engineering or a related field is required.
- Experience in pre-silicon power modeling, analysis, and power reduction, with proficiency in PTPX, Power Artist, or other power analysis tools and post-silicon power correlation
- Strong understanding of Low Power design methodologies, CPF/UPF, good understanding of physical design flow and timing closure with actual implementation experience as a plus.
- Experience developing new methodologies and transitioning those technologies to production is highly desirable.
- Knowledge in system architecture and SOC components such as CPU, fabric and peripherals
- Experience in system and on-die power integrity and EM would be an added advantage.
- Proficiency in scripting languages such as Shell, Perl or Python. Possess strong problem-solving and analytical skills.

**Key Personal and Professional Attributes

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