Design Verification Engineer

2 weeks ago


Singapore UNI CONNECT PTE LTD Full time

Bachelor/Master Degree in EEE/Computer/IC design
- 2-4 years verification experiences
- IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
- Experience and debugging ability on SystemVerilog/UVM
- Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
- Experience on Low Power and formal verification is a plus
- UNIX scripting with Pyhon, Perl, makefile Cshell



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