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Senior Staff/staff Design Verification Engineer

2 weeks ago


Singapore Silicon Labs Careers Full time

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Meet the Team

As a Design Verification Engineer, you will be responsible for ensuring the correctness and functionality of complex digital designs, particularly those involving analog and mixed-signal components. Your expertise in cosimulation will play a crucial role in verifying interactions between digital and analog blocks. Below are the key responsibilities and qualifications for this role:
Duties & Responsibilities:
- Digital AMS Cosimulation:
- Develop and maintain a cosimulation environment that allows seamless verification between digital RTL (Register Transfer Level) modules and analog/mixed-signal models (SV, Verilog A, VAMS, C/C++) or spices netlist.- Verify interactions, data exchange, and communication between these different representations of the design.- Testbench Development:
- Create System Verilog-based VMM/UVM test benches for digital components.- Specify testbench requirements and coverage plans.- Implement constrained-random sequences, agents, and environments using UVM.- Complex Verification Environments:
- Build and maintain complex and reusable verification environments using methodologies such as UVM and SystemVerilog (SV).- Write comprehensive test plans and create test benches to execute those plans.- Analyze coverage metrics, identify, and address test bench gaps, and run regressions.- File bug reports as needed.

Qualifications:
Education: A relevant degree, such as a Master’s or Bachelor’s Degree in Computer Science, Electrical Engineering, Computer Engineering, or related fields.

Skills:
- Proficiency in System Verilog, Assertion-based Formal Verification and UVM.- Familiarity with Verilog, Verilog A, C, and TCL- Knowledge of industry-standard interfaces.- Tools proficiency in Xcelium, Spectre, Questasim, Symphony- Scripting skills in languages like Python or Perl is a plus

Experience:
Ideally, 10-15 years of industry experience.

Benefits & Perks:

- You can look forward to the following benefits:_- Employee Stock Purchase Plan (ESPP)- Insurance plans with Outpatient cover- Flexible work policy

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- Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law._