Design Verification Manager
6 days ago
Responsibilities Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically and execute the plan on-time with high quality. Achieve zero-defect with the best and smartest approach to the large verification space. Qualifications Strong knowledge of SoC design principles, including IP block integration and system-level verification Experience with test plan development, execution, and analysis Familiarity with EDA tools and development flows for ASIC verification Highly disciplined, quality-minded, and highly driven for excellence. Excellent team leader and good communication skills. Strong expertise in UVM verification methodology. Experience in C and/or a scripting language such as python or perl. MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience. Experience in RTL design is a plus. Experience in video processing and video analytics is a plus. Passionate and strong in general programming is a plus. Job Details Seniority level: Not Applicable Employment type: Full-time Job function: Engineering, Design, and Management Industries: Semiconductor Manufacturing #J-18808-Ljbffr
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Design Verification Lead
3 days ago
Singapore NUWAY CFR PTE. LTD. Full time $13,200 - $39,600 per yearOne of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Lead (DV)Location : SingaporeExperience : 10+ yearsTechnical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso Knowledge of...
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Design Verification Engineer
3 days ago
Singapore NUWAY CFR PTE. LTD. Full time $90,000 - $120,000 per yearOne of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years.Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...
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Design Verification Engineer
3 days ago
Singapore tekskills Full timeYour Job Scope - Block and IP Verification - Block level verification to validate block performance and adherence to requirements - Generate and execute verification plan based on specifications - Architect and implement testbenches using UVM-based constrained-random and formal methods - Coverage definition, implementation, and analysis - Formal Verification...
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Senior Engineer
4 days ago
Singapore Future Technology Devices International Ltd Full timeDigital IC Design Verification Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with test team in debugging production test issues Help debug & correct any functional issues found in taped-out devices Participate in...
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(Sr./Staff) Design Verification Engineer
2 days ago
Singapore OmniVision Technologies Singapore Pte. Ltd. Full timeAbout the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...
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(Sr./Staff) Design Verification Engineer
6 days ago
Singapore OMNIVISION Full timeJob Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...
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Sr. Staff Engineer, Design Verification
2 weeks ago
Singapore Ambiq Full time**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...
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Sr. Staff Engineer, Design Verification
2 weeks ago
Central Singapore Ambiq Micro Full time**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...
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RTL Design Verification Engineer
3 days ago
Singapore SVENTL ASIA PACIFIC PTE. LTD. Full time $80,000 - $120,000 per yearJob Description & RequirementsDevelop verification environment and tests to perform Functional (RTL) testing at IP level and SoC LevelDevelop IP level/SoC level test plans based on the design/architectural specs.Coverage Analysis and CodingRun simulations & regressions, debug test failures to identify test case issues & RTL design issuesDefine and develop...
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Semi-Conductor Design Verification Engineer
4 days ago
Singapore REALTEK SINGAPORE PRIVATE LIMITED Full timeJOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition • Develop detailed module level and SoC level testplans for all the functional features, based on the design spec. • Develop ASIC verification environment including all the respective components such as...