Design Verification Engineer

One of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years.Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...

Responsibilities Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically...

About the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...

Job Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...

JOB DESCRIPTION: - Perform with various activities on RTL design implementation and verification at SoC level. - Responsible for RTL coding, logical synthesis, functional test plan, test bench development, RTL and gate-level simulation/verification, code coverage, formal verification, test vector generation and design documentation. - Work and provide high...

Digital IC Design Verification Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation Work with test team in debugging production test issues Help debug & correct any functional issues found in taped-out devices Participate in...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP's, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

**Company Overview**: **Staff Engineer - Design Verification** **Responsibilities**: **Specific Responsibilities**: - Must have participated in all phases of chip development, from creating test plans, creating testbench environment (SV/UVM), integrate VIP’s, automate test env for randomized testing and score boarding. - Utilize UVM to create drivers,...

Overview Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests for DUT...

**Job Descriptions** - Develop and Review Test Plan based on IC design specification - Develop constrained-Random verification environment for complex DUT - Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs - Implement coverage matrix using cover point and assertion - Create and debug tests for DUT - Resolve bugs with remote...