DFT Engineer/Lead

Roles & ResponsibilitiesJob Overview: We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan),...

Roles & Responsibilities Job Overview: We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan),...

About Bitdeer: Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment...

**Key Responsibilities**: - **DFT Architecture Design**:Lead the design of DFT architecture at the chip level, implementing testing circuits such as Scan, Mbit, Memory repair, and Bscan. - **DFT Circuit Design and Insertion**:Implement DFT circuits and integrate them into the chip, ensuring proper timing constraints for DFT mode convergence. - **Functional...

- Responsibilities: Person will be responsible for DFT Architecture including JTAG functionality, boundary scan, hierarchical scan, at - speed testing, I/ O testing requirements, MBIST and Repair, implement test logic for analog macros. Person should also be responsible to develop firmware driven cost-effective test strategies methodologies with built-in...

About the Role:As a seasoned Digital Fault Tolerance (DFT) engineer, you will be responsible for leading the technical direction and execution of DFT activities. This includes boundary scan, MBIST, test logic insertion, and JTAG implementation.You will drive the development and optimization of scan ATPG and compression methodologies to improve test coverage...

**Job Description**: - Design/verification for Clock/JTAG/Analog/DFT IP - Scan Insertion, ATPG, scan verification and pattern generation - Memory BIST insertion, validation and pattern generation - Analysis of Functional Design for Testability, including product functionality and access through external connections, BIST and Board Level Diagnostics, control...

Job Opportunity:This role involves the development and implementation of Design for Test (DFT) strategies for System-on-Chip (SoC) designs. The ideal candidate will have a strong understanding of DFT principles, experience working with DFT EDA tools, and excellent collaboration and communication skills.Key Responsibilities:Develop and implement DFT...

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products. **Senior Staff Engineer - Design For Test (DFT) **Responsibilities**: - Responsible for scan insertion,...

DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST - Analysis to improve the testability of Digital design at Block and chip level. - Implementation of DFT logics for Digital and Mixed Signal IP. - Perform ATPG pattern generation / Verification including SSA /Transition/ Path Delay and IDDQ pattern. - Deliver high quality ATE patterns for...