Senior Low-Power Physical Design Engineer
20 hours ago
About the Role
SUNLUNE (SINGAPORE) PTE. LTD. is seeking an experienced Senior Low-Power Physical Design Engineer to join our team. As a key member of our design team, you will be responsible for designing and optimizing low-power ICs from concept to tape-out.
Responsibilities
- Low-Power Design Workflows: Own the design process to minimize power consumption while ensuring performance and reliability using advanced tools and techniques.
- Full-Chip Floor Planning and Routing: Lead floor planning and place-and-route efforts to optimize chip area and meet performance, area, and power goals.
- Power Network Design: Create and analyze robust power networks to ensure performance, minimize losses, and support low-power goals.
- Timing Closure and Signoff: Collaborate with teams to resolve timing issues and manage power and signal integrity for design verification.
- Physical Verification (DRC and LVS): Ensure compliance with layout and manufacturing rules through DRC and LVS for a tape-out-ready design.
- Cross-Team Collaboration: Work with engineers across functions to align designs with chip architecture and solve design challenges.
- Continuous Improvement: Stay updated on design advancements and improve workflows for better efficiency and low-power optimization.
Requirements
- Educational Background: Bachelor's degree or higher in Electronics, Computer Science, Electrical Engineering, or a related field. Advanced degrees (Master's/Ph.D.) are a plus.
- Experience: Minimum X years in physical design with a focus on high-performance, low-power designs. Must have tape-out experience and familiarity with advanced semiconductor technologies (12nm and below).
- Technical Expertise: Proficient in full-chip floor planning, place-and-route, and physical verification (DRC and LVS). Strong knowledge of power network design, IR drop analysis, and timing closure with static timing analysis (STA) tools like PrimeTime.
- Software Knowledge: Experience with tools such as Synopsys IC Compiler, Cadence Innovus, and scripting languages like Perl, TCL, and Python.
- Place-and-Route Experience: Hands-on expertise in place-and-route methodologies for optimizing performance, power, and area.
- Soft Skills: Excellent communication and collaboration skills to work effectively in multidisciplinary teams. Strong problem-solving and critical thinking abilities to address design challenges.
- Preferred Skills: Experience with advanced low-power techniques, deep sub-micron technologies (7nm, 5nm, etc.), multi-voltage designs, and design-for-manufacturing (DFM) principles.
Salary and Benefits
The estimated salary for this role is around SGD $120,000 - SGD $180,000 per annum, depending on experience. We offer a comprehensive benefits package, including medical insurance, retirement plans, and paid time off.
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