Senior Physical Design Lead

12 hours ago


Singapore SUNLUNE (SINGAPORE) PTE. LTD. Full time

We are looking for a Senior Physical Design Engineer to join our team at SUNLUNE (SINGAPORE) PTE. LTD.

Job Description

The ideal candidate will have 10+ years of experience in physical design with expertise in high-performance, low-power semiconductor technologies (12nm and below). Proven tape-out success and leadership experience are essential.

Key Responsibilities:
  • Strategize and Lead Low-Power Design Initiatives: Define and execute strategies for achieving low-power, high-performance physical design. Lead the development of innovative workflows and methodologies to minimize power consumption while ensuring design reliability and scalability.
  • Oversee Full-Chip Floor Planning and Routing: Provide technical leadership in full-chip floor planning and place-and-route activities. Optimize chip area, performance, and power metrics, while mentoring junior engineers in advanced methodologies.
  • Architect Power Distribution Networks: Design and validate robust power networks to meet demanding performance criteria. Conduct power integrity analysis to address IR drop, noise, and power grid optimization, ensuring alignment with low-power objectives.
  • Drive Timing Closure and Integrity Signoff: Lead timing closure efforts across cross-functional teams. Address complex timing violations, optimize critical paths, and ensure successful power and signal integrity signoff for final design verification.
  • Champion Physical Verification Processes: Oversee DRC and LVS verification, resolving escalated issues and ensuring designs comply with layout and manufacturing rules. Guide the team through pre-tape-out readiness.
  • Facilitate Cross-Team Collaboration: Act as a key liaison among RTL, analog, and verification teams. Drive alignment between physical design and overall architecture while addressing challenges and providing technical guidance to stakeholders.
  • Promote Continuous Improvement: Champion the adoption of emerging tools, techniques, and methodologies. Drive workflow innovations to enhance efficiency, scalability, and quality of low-power physical design.
Requirements

To be considered for this role, you should have the following qualifications:

  • Educational Background: Bachelor's degree in Electronics, Computer Science, Electrical Engineering, or a related field. Master's or Ph.D. preferred.
  • Experience: 10+ years in physical design with expertise in high-performance, low-power semiconductor technologies (12nm and below). Proven tape-out success and leadership experience are essential.
  • Advanced Technical Expertise: Deep expertise in full-chip floor planning, place-and-route, and physical verification (DRC and LVS). Advanced knowledge of power network architecture, IR drop, and noise analysis. Strong proficiency with timing closure processes and STA tools like PrimeTime.
  • Software and Tools Proficiency: Extensive experience with industry-standard tools such as Synopsys IC Compiler, Cadence Innovus, and scripting languages like Perl, TCL, and Python.
  • Place-and-Route Leadership: Expert-level experience in advanced place-and-route strategies for performance and power optimization.
  • Leadership and Mentorship: Proven ability to lead teams, mentor junior engineers, and manage cross-disciplinary collaboration in a fast-paced environment.

Estimated salary: SGD 120,000 - SGD 180,000 per annum.



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