Chip Physical Design Engineer

Roles & ResponsibilitiesJob Responsibilities: Develop Low-Power Design Workflows:Own the design process to minimize power consumption while ensuring performance and reliability using advanced tools and techniques. Full-Chip Floor Planning and Routing:Lead floor planning and place-and-route efforts to optimize chip area and meet performance, area, and power...

Roles & ResponsibilitiesJob Responsibilities: Develop Low-Power Design Workflows:Own the design process to minimize power consumption while ensuring performance and reliability using advanced tools and techniques. Full-Chip Floor Planning and Routing:Lead floor planning and place-and-route efforts to optimize chip area and meet performance, area, and power...

About the RoleALPSOFT TECHNOLOGIES PTE. LTD. is seeking a highly skilled Senior Physical Design Engineer to lead our team in implementing advanced process chip designs.Key ResponsibilitiesFull responsibility for netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips.Block owner, taking ownership of blocks with 2~3...

Job DescriptionWe are seeking a highly skilled Digital Design Expert to join our team at ESPRESSIF SYSTEMS (SINGAPORE) PTE. LTD.Key Responsibilities:Develop and implement advanced chip physical design techniques for full-chip/block covering floor planning, placement, area optimization, clock tree synthesis, routing, timing closure, power network design, and...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

Job Summary:At SUNLUNE (SINGAPORE) PTE. LTD., we are seeking an experienced Senior Low Power Physical Design Engineer to join our team in developing cutting-edge chip designs.About the Role:This is a unique opportunity for a highly skilled engineer to lead the development of advanced low-power physical design and integration flows, driving innovation in...

At LEADTOP TECHNOLOGY PTE. LTD., we are seeking a highly skilled Backend Design Engineer to join our team in Singapore. With a competitive salary and compensation package, this role offers excellent opportunities for growth and development.Company OverviewWe are a chip design service company invested by an international consortium and founded by a senior...

Job SummaryMANPOWER STAFFING SERVICES (SINGAPORE) PTE LTD seeks a Senior Physical Design Engineer to lead the physical design process for complex semiconductor chips. As a key member of our team, you will be responsible for the entire process from RTL to GDS, ensuring successful implementation of complex semiconductor chips.Key Responsibilities:Lead the...

Roles & ResponsibilitiesResponsibilities: · Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. · Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff · Block coordinator role for more than 5~10...

Roles & ResponsibilitiesPosition Overview: We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low...

Roles & ResponsibilitiesJob Description：1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .2. Takes charge of the physical design tasks from the Netlist to the GDS2, including formal verification, static timing analysis, physical verification, power analysis, design for reliability (DFR) and...

Roles & ResponsibilitiesJob Description：1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .2. Takes charge of the physical design tasks from the Netlist to the GDS2, including formal verification, static timing analysis, physical verification, power analysis, design for reliability (DFR) and...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power...

Responsibilities:Fully responsible for Netlist-to-GDS physical design implementation of low power chipsRequirements:Bachelor/Masters Degree in Electrical/Computer EngineeringExperience in physical design with tape-outsKnowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or EncounterGood in script programming with Perl, TCL/TK or other...

Job DescriptionXilinx Asia Pacific PTE. LTD. is seeking a skilled Silicon Design Engineer to join their team as a Chip Integration Specialist.About the Role:This role involves working with various engineering groups to achieve physical and electrical verification of AMD SoC FPGA/ACAP devices.Key Responsibilities:Developing methodologies for chip-level...

Roles & ResponsibilitiesResponsibilities: Fully responsible for Netlist-to-GDS physical design implementation of low power chipsRequirements: Bachelor/Masters Degree in Electrical/Computer Engineering Experience in physical design with tape-outs Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter Good in script...

Roles & ResponsibilitiesResponsibilities: Fully responsible for Netlist-to-GDS physical design implementation of low power chipsRequirements: Bachelor/Masters Degree in Electrical/Computer Engineering Experience in physical design with tape-outs Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter Good in script...

Roles & ResponsibilitiesResponsibilities: Fully responsible for Netlist-to-GDS physical design implementation of low power chipsRequirements: Bachelor/Masters Degree in Electrical/Computer Engineering 3-6 yrs Experience in physical design with tape-outs Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter Good in...

Roles & ResponsibilitiesResponsibilities: Fully responsible for Netlist-to-GDS physical design implementation of low power chipsRequirements: Bachelor/Masters Degree in Electrical/Computer Engineering 3-6 yrs Experience in physical design with tape-outs Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter Good in...