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Advanced NAND Design Rule Engineer
3 weeks ago
We're seeking a talented engineer to join our team as a NAND Design Rule Engineer in Process Integration. This is a crucial role that requires expertise in advanced NAND process flows, design rules, and layout techniques.
The ideal candidate will have experience in semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development. They should be familiar with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE, and have a proven track record of resolving sophisticated issues.
This role involves driving and contributing to next generation Advanced NAND development efforts, working with multiple peer groups to define, implement, and coordinate effective actions to enable multiple projects to hit key achievements and timelines.
- Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production Designs
- Drive/Contribute to deliver key milestones starting from Project Kick Off till End of Life
- Collaborate with stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to direct development efforts for a new Advanced NAND generation
- Ensure quality of DRCs released with appropriate reaction to deviation from established design rules and proper documentation
- Work with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design
- Help design and evaluate test structures to provide data for next generation devices and quantify process margin on current devices
- Summarize complex problems, derive, and explain actions taken to address them
- Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment
- Define sub-milestones for the project within the layout schedule and work with various teams to achieve targets and timelines
- Ensure best possible communication between NAND Design Rule and other key stakeholders
- Enthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques
To succeed in this role, you will need to possess strong analytical skills, excellent communication abilities, and the ability to work effectively in a team environment.
We are committed to helping you grow and develop your career, offering competitive compensation and benefits package.
About Micron Technology
We are a leading innovator in memory and storage solutions, transforming how the world uses information to enrich life for all.
Finding innovative solutions to real-world challenges drives everything we do.
As a NAND Design Rule Engineer in Process Integration, you will play a vital role in advancing our cutting-edge technology, collaborating with cross-functional teams to drive business growth and improve customer satisfaction.
