
Hardware Architectural Expert
1 week ago
School of Electrical and Electronic Engineering is one of the founding schools of a renowned university. Built on a culture of excellence, the school is recognized for its high academic standards and research.
With over 3,000 undergraduate students and 1,000 graduate students, it is one of the largest EEE schools in the world and ranks 10th in the field of Electrical & Electronic Engineering in the QS World University Rankings by Subjects.
The school has become one of the world's largest engineering schools that nurtures competent engineers and researchers. Each year, the school graduates over a thousand students who are ready to take on great ambitions and challenges.
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We are looking for a highly skilled Hardware Architectural Expert with experience in RISC-V architecture. The successful candidate will be responsible for adding a Hardware AES and ASCON Accelerator to the RISC-V CVA6 core.
This role requires deep knowledge of hardware design, cryptographic algorithms, and the RISC-V instruction set architecture (ISA). You will work closely with the AES and ASCON designers in our team to ensure seamless integration and optimal performance of the cryptographic accelerators.
- Design and Implementation:
- Integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator into the RISC-V CVA6 (Ariane) core.
- RISC-V ISA Extension:
- Define and implement custom RISC-V instructions to utilize the AES and ASCON hardware accelerators, if needed.
- Verification and Testing:
- Conduct simulations to evaluate the performance, latency, and throughput of the accelerators within the CVA6 pipeline.
Job Requirements:
Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.
Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design.
Proficiency in toolchain modification, including the ability to extend assemblers and compilers (GCC, LLVM) for custom hardware instructions.
Proficiency of FPGA development tools such as Vivado, Quartus, or similar for prototyping.
Strong understanding of ASIC/FPGA design flows, including synthesis, place and route, and timing closure.
Experience in cryptography and implementing cryptographic algorithms in hardware (AES, ASCON, etc.).
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