AI ASIC Engineer IC Design Entry-Level

Roles & ResponsibilitiesRESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO:• Develop microarchitecture and RTL design and verification for Expedera AI accelerators• Explore microarchitecture and architecture for design space optimization (power/performance/area)• Collaborate with HW/SW architects in HW specification process, HW/SW co-design• Execute...

This will be a permanent position based in Jurong East There are 4 open positions: SoC Architecture Scope of Work Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Work on SoC floorplan with architect and APR; SoC...

Roles & Responsibilities Responsible for RTL design, simulation, and verification for ASIC/SoC products. Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team. Create reusable internal IPs for AI and/or in-memory computing products. Handle IP integration and validation and support post-Si...

Job Description:Responsible for analog/hybrid circuit program planning and design implementation, performance optimization, simulation verification and testing related workResponsible for the design of high-performance, ultra-low voltage customized circuits under advanced technology. Targeting specific PPA requirements, able to select transistors,...

Responsibilities:The Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc .The responsibility of the...

Roles & ResponsibilitiesResponsibilities: The Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs, including the required amplifiers, ADCs, filters and control logic, with characteristic high impedance inputs, ultra low power, low noise circuits etc . ...

Roles & ResponsibilitiesJOB DESCRIPTION· Discussion with system engineers on SoC architecture and feedback on optimization.· Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Discussion with synthesis engineer and back-end engineer on design optimization.· SoC DFT...

Roles & ResponsibilitiesJOB DESCRIPTION· Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;· Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support;...

Roles & ResponsibilitiesKey Responsibilities: Working on ASIC digital design, including RTL coding based on Verilog, simulation, RTL and gate-level verification, code coverage, testbench development, logic synthesis, and design documentation.Key Requirements: Master/Degree in Electrical Engineering with 3 years of ASIC design. experience preferred. ...

Roles & ResponsibilitiesJOB DESCRIPTION· Work with system engineers on timing requirements and feedback on optimization.· Work on SoC timing constraint, synthesis and timing closure.· Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains· Conduct formal verification for release comparison.· Support back-end...

Roles & ResponsibilitiesPosition Overview: The Staff/Senior Design Engineer will be responsible for developing micro-architecture for Image Signal Processing Unit (ISP) and Computer Vision Unit (CV) related algorithms. They will utilize RTL design using Verilog/System Verilog coding and High-Level Synthesis (HLS) tools like Catapult. Additionally, they will...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs...

Roles & ResponsibilitiesJob Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches using UVM/SystemVerilog for Pre-Silion IP or SOCs Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with...

Roles & ResponsibilitiesJOB DESCRIPTION· Discussion with system engineers on IP requirement and micro architecture.· Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.· Support SoC designer on integration, timing constraints and power domain setting.· Support IP verification for verification plan...

Roles & ResponsibilitiesKey responsibilities: Perform IC design of FTDI products Perform Verilog RTL design to meet product specifications and requirements Perform front-end verification using UV methodology Work with Systems and Software engineers on FPGA verification Perform Logic Synthesis, Static Timing Analysis Lead DFT related activities - Scan...

Responsible for RTL design, simulation, and verification for ASIC/SoC products.Identify internal and external requirements, PPA study, RTL coding, implementation and work closely with backend team.Create reusable internal IPs for AI and/or in-memory computing products.Handle IP integration and validation and support post-Si testing and...

Roles & ResponsibilitiesResponsibilities: Collaborate with Senior Engineers for design requirements and specifications. Assist in Analog, mixed-signal, and digital IC design. Participate in RTL coding and verification for digital ICs. Support design verification tasks. Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics...

Roles & ResponsibilitiesDigital IC Verification Develop and maintain verification environment for IP modules and SOC level using UVM methodology. Write, review and implement verification plan. Create and debug test cases. Perform code coverage analysis on IP modules and SOC level. Continuous improvement of the verification flow.Additional...

Roles & ResponsibilitiesResponsibilities Work with MEMS Research & Development, ASIC design team & Packaging team to perform failure analysis in root cause finding for improvement or issue investigation. In-charge of failure analysis request from internal customers and external customers for customer returns, production/process rejects, and...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...