Senior (Staff ) Physical Design/IC Backend Design Engineer

Roles & ResponsibilitiesA chip design service company invested by an international consortium and founded by a senior chip design technical team. The company is headquartered in Singapore and will take root in Singapore for long-term development. The company has strong R&D capabilities, and its core technical team members all have more than 10 years of...

Roles & ResponsibilitiesA chip design service company invested by an international consortium and founded by a senior chip design technical team. The company is headquartered in Singapore and will take root in Singapore for long-term development. The company has strong R&D capabilities, and its core technical team members all have more than 10 years of...

IC Design Engineer/ IC Physical Design Engineer #74185Job DescriptionIndustry/ Organization Type: SemiconductorPosition Title: IC Design Engineer/ IC Physical Design EngineerWorking Location: Jurong East (close to Jurong East MRT)Working Hours: Monday – Friday, 9am – 6pmSalary Package: Basic + AWS + Performance BonusDuration: PermanentKey...

Roles & ResponsibilitiesJob role:1. Works with the front-end design team to complete the chip floorplan , clockarchitecture, and powerplan .2. Takes charge of the physical design tasks from the Netlist to the GDS2, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability (DFR) and tapeout.3....

Roles & ResponsibilitiesJob Description: IC physical design of 6nm/4nm/3nm and below world leading advanced process chip, from RTL to GDS. Block/Macro execution role for Synthesis/APR/PV tasks, solving the critical issue and give the solution to other block owners. TOP role for the complicated hierarchical chip (more than 20 million instances plus 1000+...

Roles & ResponsibilitiesJob Description: IC physical design of 6nm/4nm/3nm and below world leading advanced process chip, from RTL to GDS. Block/Macro execution role for Synthesis/APR/PV tasks, solving the critical issue and give the solution to other block owners. TOP role for the complicated hierarchical chip (more than 20 million instances plus 1000+...

Roles & ResponsibilitiesJob DescriptionDesign and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing...

Roles & ResponsibilitiesJob DescriptionWorking on 6nm and below advanced process project APR and Timing/PI sign-off Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros) Take the Block or Block coordinator role for complex blocks Do early prediction for critical APR/Timing/PI issuesJob...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power...

Roles & ResponsibilitiesJob DescriptionWe have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible for developing the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier service providers. Our IC R&D team is looking for an...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power...

Roles & ResponsibilitiesPosition Overview:We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power...

Roles & ResponsibilitiesWe have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible fordeveloping the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier serviceproviders. Our IC R&D team is looking for an experienced physical design...

Roles & ResponsibilitiesJob DescriptionIndustry/ Organization Type: Semiconductor Position Title: IC Design Engineer/ IC Physical Design Engineer Working Location: Jurong East (close to Jurong East MRT) Working Hours: Monday – Friday, 9am – 6pm Salary Package: Basic + AWS + Performance Bonus Duration: PermanentKey ResponsibilitiesDevelop analog IC...

Roles & ResponsibilitiesJob Description Industry/ Organization Type: Semiconductor Position Title: IC Design Engineer/ IC Physical Design Engineer Working Location: Jurong East (close to Jurong East MRT) Working Hours: Monday – Friday, 9am – 6pm Salary Package: Basic + AWS + Performance Bonus Duration: PermanentKey Responsibilities Develop analog...

Roles & ResponsibilitiesJob DescriptionDesign and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing...

Roles & ResponsibilitiesResponsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement...

Roles & ResponsibilitiesResponsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement...

Roles & ResponsibilitiesResponsibilityResponsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement fixes...

Roles & ResponsibilitiesJob Responsibilities: Strategize and Lead Low-Power Design Initiatives:Define and execute strategies for achieving low-power, high-performance physical design. Lead the development of innovative workflows and methodologies to minimize power consumption while ensuring design reliability and scalability. Oversee Full-Chip Floor...