physical design engineer trainee

Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the requirements....

Netlist to GDSII at block level, Subsystem Level and at Full chip. . Worked on multiple tapeouts on Netlist to GDSII . Hierarchical partitioning and budgeting of block-level subsystems. . Implementation of high performance (HP) cores, low power designs . Node experience upto 7nm, 10nm, 14nm, 28nm. . Timing Signoff in loop through STA and ECO cycle at block...

1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3....

Responsibility: 1. Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.2. Multiple tasks including but not limited to: back-end physical implementation from gate-level...

Join us as we work together to inspire creativity and enrich life around the globe.Location:Team:TechnologyEmployment Type:RegularJob Code:A70775AShare this listing:ResponsibilitiesTeam IntroductionThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™...

Job Description & Requirements Netlist to GDSII at block level, Subsystem Level and at Full chip. Worked on multiple tapeouts on Netlist to GDSII Hierarchical partitioning and budgeting of block-level subsystems. Implementation of high performance (HP) cores, low power designs Node experience upto 7nm, 10nm, 14nm, 28nm. Timing Signoff in loop through STA and...

About Us Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create...

Responsibilities: Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners. TOP...

Position Overview We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

Responsibilities: Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners. TOP...

About Us Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create...

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This...

About Bitdeer:Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes...

Position Overview We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This...

ResponsibilityResponsible for high-performance block implementation (RTL to GDSII).Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing.Close the design to meet timing, power budget and area targets.Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the...

Job Description Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoCdesigns using industry-leading EDA tools and AI-assisted methodologies, Develop and execute synthesis, Design-for-Test (DFT), and timing closure strategies, including DRC/LVS, static timing analysis (STA), scan/DFT validation, and GDS tape-out verification, leveraging...

Job De ion Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing Analysis s using...

Job Description Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoCdesigns using industry-leading EDA tools and AI-assisted methodologies, Develop and execute synthesis, Design-for-Test (DFT), and timing closure strategies, including DRC/LVS, static timing analysis (STA), scan/DFT validation, and GDS tape-out verification, leveraging...