physical design engineer trainee

Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the requirements....

ResponsibilityResponsible for high-performance block implementation (RTL to GDSII).Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing.Close the design to meet timing, power budget and area targets.Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the...

Job Responsibilities Possess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification. Job Requirements Bachelor's degree with minimum 3 years of relevant working experience. Solid hands‑on physical‑design back‑end experience....

1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3....

Job ResponsibilitiesPossess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification.Job RequirementsBachelor's degree with minimum 3 years of relevant working experience.Solid hands‑on physical‑design back‑end experience. Familiar...

1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3....

Responsibility:1. Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.2. Multiple tasks including but not limited to: back-end physical implementation from gate-level...

Roles & Responsibilities Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. Close the design to meet timing, power budget and area targets. Run physical verification flows (DRC/LVS/EM/IR), and...

Roles & Responsibilities Netlist to GDSII at block level, Subsystem Level and at Full chip. • Worked on multiple tapeouts on Netlist to GDSII • Hierarchical partitioning and budgeting of block-level subsystems. • Implementation of high performance (HP) cores, low power designs • Node experience upto 7nm, 10nm, 14nm, 28nm. • Timing Signoff in...

Join us as we work together to inspire creativity and enrich life around the globe. Location: Team: Technology Employment Type: Regular Job Code: A70775A Share this listing: Responsibilities Team IntroductionThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip...

Responsibilities Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR...

Netlist to GDSII at block level, Subsystem Level and at Full chip. . Worked on multiple tapeouts on Netlist to GDSII . Hierarchical partitioning and budgeting of block-level subsystems. . Implementation of high performance (HP) cores, low power designs . Node experience upto 7nm, 10nm, 14nm, 28nm. . Timing Signoff in loop through STA and ECO cycle...

Roles & Responsibilities Netlist to GDSII at block level, Subsystem Level and at Full chip. • Worked on multiple tapeouts on Netlist to GDSII • Hierarchical partitioning and budgeting of block-level subsystems. • Implementation of high performance (HP) cores, low power designs • Node experience upto 7nm, 10nm, 14nm, 28nm. • Timing Signoff in loop...

ResponsibilitiesBlock-level physical design of large-scale AI chip (Netlist to GDS out) for tapeout. Optimize timing, power, area, etc. Responsible for backend analysis: timing, power, power integrity, signal integrity, etc. Responsible for physical verification including DRC, LVS, ERC, Latchup, etc.Qualifications Bachelor's degree and above in Electrical...

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This...

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™...

We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for...

Responsibilities The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...

About the role Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and PD/Integration teams across our China and Taiwan offices to drive successful tape outs. Why Credo Purpose: We invest in...