physical design

Netlist to GDSII at block level, Subsystem Level and at Full chip.- Worked on multiple tapeouts on Netlist to GDSII- Hierarchical partitioning and budgeting of block-level subsystems.- Implementation of high performance (HP) cores, low power designs- Node experience upto 7nm, 10nm, 14nm, 28nm.- Timing Signoff in loop through STA and ECO cycle at block and at...

Responsibility Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging. Multiple tasks including but not limited to: back-end physical implementation from gate-level...

Physical Design Engineer About the Role Join a global leader in chip design and high end IC components. We are looking for Physical Design Engineers of different seniority levels to implement digital circuits and design flows. Key Responsibilities Lead the end-to-end digital backend execution (from netlist to GDSII), driving full-chip static timing...

>Job Responsibilities Possess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification. Job Requirements Bachelor’s degree with minimum 3years of relevant working experience. Solid hands‑on physical‑design back‑end experience....

Requirement 1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA...

Physical Design Engineer About the Role Join a global leader in chip design and high end IC components. We are looking for Physical Design Engineers of different seniority levels to implement digital circuits and design flows. Key Responsibilities Lead the end-to-end digital backend execution (from netlist to GDSII), driving full-chip static timing analysis....

Netlist to GDSII at block level, Subsystem Level and at Full chip. - Worked on multiple tapeouts on Netlist to GDSII - Hierarchical partitioning and budgeting of block-level subsystems. - Implementation of high performance (HP) cores, low power designs - Node experience upto 7nm, 10nm, 14nm, 28nm. - Timing Signoff in loop through STA and ECO cycle at block...

>Job ResponsibilitiesPossess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification.Job RequirementsBachelor’s degree with minimum 3years of relevant working experience.Solid hands‑on physical‑design back‑end experience. Familiar...

Physical Design Engineer About the Role Join a global leader in chip design and high end IC components. We are looking for Physical Design Engineers of different seniority levels to implement digital circuits and design flows. Key Responsibilities Lead the end-to-end digital backend execution (from netlist to GDSII), driving full-chip static timing...

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This...

Company OverviewBroadcom Inc. is a global technology leader designing and supplying semiconductor and infrastructure software solutions. Its products serve data center, networking, software, broadband, wireless, storage, and industrial markets. More info at www.broadcom.com.Job SummaryDesign and implement advanced integrated circuits using cutting-edge...

Job Description: Skills and Responsibilities: Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for thedesignand implementation of 100~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies. Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis,...

ResponsibilitiesThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic...

Job Description Responsible for physical design, development for variety of SoC(System On Chip) and tapeout. Execute state-of-art methodologies include, floor-planning, place and route, RC extraction, timing and power optimization, physical verification. Doing benchmarking on Performance/Power/Area to validate the robustness of APR flow. Enhance project...

Company Overview Broadcom Inc. is a global technology leader designing and supplying semiconductor and infrastructure software solutions. Its products serve data center, networking, software, broadband, wireless, storage, and industrial markets. More . Job Summary Design and implement advanced integrated circuits using cutting-edge process technologies....

Company Overview Broadcom Inc. is a global technology leader designing and supplying semiconductor and infrastructure software solutions. Its products serve data center, networking, software, broadband, wireless, storage, and industrial markets. More . Job Summary Design and implement advanced integrated circuits using cutting-edge process technologies....

Job Description Skills and Responsibilities Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies. Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis,...

Job Description: Skills and Responsibilities: Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for thedesignand implementation of 100~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies. Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis,...

Responsibilities The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™...