physical design

ResponsibilityResponsible for high-performance block implementation (RTL to GDSII).Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing.Close the design to meet timing, power budget and area targets.Run physical verification flows (DRC/LVS/EM/IR), and implement fixes to meet the...

Netlist to GDSII at block level, Subsystem Level and at Full chip. . Worked on multiple tapeouts on Netlist to GDSII . Hierarchical partitioning and budgeting of block-level subsystems. . Implementation of high performance (HP) cores, low power designs . Node experience upto 7nm, 10nm, 14nm, 28nm. . Timing Signoff in loop through STA and ECO cycle...

About the Company We are a fast-growing semiconductor company specialising in VLSI and embedded systems, with operations spanning Singapore and ASEAN. Our team designs high-performance data processing chips and delivers high-quality ASIC design services, combining advanced technology with product innovation to build robust, value-driven solutions for...

PHYSICAL DESIGN MANAGER | SEMICONDUCTOR & ASIC DESIGN (SINGAPORE) Our engineering group owns the full RTL-to-GDSII flow for a fast-scaling semiconductor company focused on VLSI and embedded systems, producing high-performance data-processing chips and premium ASIC design services for the information-security space. As demand grows, we're expanding a...

Responsibilities Block-level physical design of large-scale AI chip (Netlist to GDS out) for tapeout. Optimize timing, power, area, etc. Responsible for backend analysis: timing, power, power integrity, signal integrity, etc. Responsible for physical verification including DRC, LVS, ERC, Latchup, etc. Qualifications Bachelor's degree and...

Job Responsibilities Possess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification. Job Requirements Bachelor's degree with minimum 3 years of relevant working experience. Solid hands‑on physical‑design back‑end...

Responsibility: 1. Responsible for the physical design of advanced process digital ASIC/AI/CPU chips, layout design of analog/digital chips, PPAC optimization under advanced processes, fully custom design, and exploration of new technologies in advanced packaging.2. Multiple tasks including but not limited to: back-end physical implementation from gate-level...

Responsibilities Block-level physical design of large-scale AI chip (Netlist to GDS out) for tapeout. Optimize timing, power, area, etc. Responsible for backend analysis: timing, power, power integrity, signal integrity, etc. Responsible for physical verification including DRC, LVS, ERC, Latchup, etc. Qualifications Bachelor's degree and...

About the CompanyWe are a fast-growing semiconductor company specialising in VLSI and embedded systems, with operations spanning Singapore and ASEAN. Our team designs high-performance data processing chips and delivers high-quality ASIC design services, combining advanced technology with product innovation to build robust, value-driven solutions for...

1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3....

About Us Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create...

Salary: SGD10,000SGD13,500/ per month (Negotiable) Benefits: Guaranteed 14-Month Package + Performance Bonus Why Join Voice The Way (VTW) We are looking for experienced engineers who want to focus on technical challenges without being bogged down by office politics. Top-Tier Rewards: We provide a market-leading salary package, including...

Responsibilities Maxlinear is seeking a Principal Physical Design Engineer (SoC Middle-End - RTL2NETLIST) to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below and focusing on: Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding...

Position Overview We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power...

About the role Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and PD/Integration teams across our China and Taiwan offices to drive successful tape outs. Why Credo Purpose: We invest in...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™...

Responsibilities The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...

Responsibilities Maxlinear is seeking a Principal Physical Design Engineer (SoC Middle-End - RTL2NETLIST) to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below and focusing on: Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding...

About the role Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and PD/Integration teams across our China and Taiwan offices to drive successful tape outs. Why Credo Purpose: We invest in...

Responsibilities:Full responsible for Netlist-to-GDS physical design implementation of 12nm/6nm/4nm and below advanced process chips. Block owner, take block of 23 Million instances, working on Synthesis/APR(auto place and route)/Signoff Block coordinator role for more than 510 blocks, solving the critical issue and give the solution to block owners. TOP...