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AUREXIS TECH PTE. LTD. is seeking a circuit-layout engineer in Singapore with 3+ years of experience to design and own layouts for analog, digital and mixed-signal circuits. You will collaborate with analog designers on floorplanning and layout implementation, performing comprehensive DRC/LVS/ERc/ESD checks and ensuring timely milestones. Proficiency in...

VisionPower Semiconductor Manufacturing Company Pte Ltd (VSMC) in Singapore seeks an EHS professional to identify, assess and advise on risks arising from workplace health, environment and processes, and to implement measures to minimize and control them. You will conduct hazard assessments, drive EHS compliance across fab operations, manage waste, air,...

Bitmain in Singapore is seeking an IC layout design engineer to drive layout planning for analog and mixed-signal circuits. You will independently perform DRC, LVS, ERC and other verification tasks while collaborating with analog design engineers to optimize layouts. You will also prepare and maintain documentation to support design activities. The ideal...

Bitmain in Singapore is seeking an IC layout engineer to plan and design analog and mixed-signal circuit layouts, collaborating with circuit designers to optimize placements and routing. The role involves performing DRC, LVS, ERC verification and maintaining technical documentation, with a focus on 8nm or smaller nodes. SRAM layout experience is a plus, and...

PERSOL Singapore is seeking an experienced IC Design Engineer in Singapore to code and maintain DRC/LVS/ANT/ERC/LPE/ESD decks and develop physical verification flows. You will collaborate with the PDK team and QA to reduce defects and contribute to automation through scripting in Tcl, Perl, and C-shell. The role requires 8+ years in IC design, experience...

MediaTek Singapore Pte Ltd is seeking a motivated Physical Verification engineer to define and deliver sign-off flows for advanced SoC design. You will collaborate with PDK, DFM, MF and Designers to code and maintain DRC/LVS/ANT/DMY/ERC rule decks across processes and develop robust layout and PV flows. You will also work with QA to reduce defects, perform...

Broadcom Inc. in Singapore is seeking a skilled IC Layout Engineer to execute high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP in advanced nodes. You will manage layout schedules from transistor level to floorplanning, collaborate across sites, and use Cadence Virtuoso with Calibre for DRC/LVS/ERC analysis; knowledge of 5nm+ nodes and...

PERSOL is seeking an experienced IC Design Verification Engineer in Singapore to join our team and work on DRC, LVS, ERC, LPE and ESD rule decks for multiple processes. You will develop layout implementation and physical verification flows, collaborating with QA to reduce PDK defects and performing full-chip verification. Strong scripting skills...

Responsible for layout planning and design of analog and mixed-signal circuit modules; Independently perform DRC, LVS, ERC, and other layout verification tasks; Work closely with analog circuit design engineers to ensure effective communication and layout optimization; Prepare and maintain relevant technical documentation. RequirementBachelor’s degree or...

Business Function Group Technology enables and empowers the bank with an efficient, nimble, and resilient technology infrastructure through a strategic focus on innovation, engineering excellence, productivity, quality, and control. We partner closely with our business stakeholders to deliver secure and scalable digital solutions that support the bank’s...

Job Description Co-work with PDK team to code and maintain DRC / LVS / ANT / ERC / LPE / ESD rule deck for various processes Develop layout implementation flow and physical verification flow Co-work with QA team to reduce the PDKs/Rule deck defect Perform full-chip physical verification such as debugging DRC / LVS / ERC Implement automation scripts in...

Business Function Group Technology enables and empowers the bank with an efficient, nimble, and resilient technology infrastructure through a strategic focus on innovation, engineering excellence, productivity, quality, and control. We partner closely with our business stakeholders to deliver secure and scalable digital solutions that support the bank’s...

Job DescriptionResponsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT,ERC, ESD, PERC) for tape-out Co-work with Place & Route team to resolve full-chip layout integration issues Coordinates with internal IP owners on IP related issues Coordinates with Manufacturing Team on DRC related issues Provide automation solutions to...

Business Function Group Technology enables and empowers the bank with an efficient, nimble, and resilient technology infrastructure through a strategic focus on innovation, engineering excellence, productivity, quality, and control. We partner closely with our business stakeholders to deliver secure and scalable digital solutions that support the bank's...

Job Description:Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out. Co-work with Package Design Team to resolve multi-dies integration issues. Co-work with ESD Team to run 3D_PERC flow. Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD) Provide automation solutions...

Job Description Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation...

Job Description: Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out. Co-work with Package Design Team to resolve multi-dies integration issues. Co-work with ESD Team to run 3D_PERC flow. Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD) Provide automation solutions...

Job Description Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation...

Job Responsibilities:Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.Co-work with Place & Route team to resolve full-chip layout integration issues.Coordinates with internal IP owners on IP related issues.Coordinates with Manufacturing Team on DRC related issues.Provide automation solutions...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™...