Physical Design Engineer
2 weeks ago
Job Description: Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing; Drive timing closure, formal verification, low-power analysis, and power optimization; Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD checks; Support cross-functional integration and validation between frontend and backend design teams; Contribute to the development and refinement of backend flows for advanced process technologies. Requirements: Master’s degree or higher in Microelectronics, IC Design, Electrical Engineering, Computer Engineering, or a related field; 5–10+ years of hands-on experience in digital backend design for ASIC or SoC products; Proven experience with advanced technology nodes such as 3nm, 4nm, or 6nm, with successful tape-out records; Strong background working with major foundries such as TSMC or Samsung at either block-level or full-chip scale; Proficient with industry-standard EDA tools, including Cadence and/or Synopsys platforms for P&R, STA, and physical verification; Deep expertise across the full backend flow—from netlist to GDSII—including floorplanning, power planning, placement, optimization, CTS, routing, ECO implementation, RC/SPEF extraction, and STA sign-off; Solid grasp of static timing analysis and low-power design techniques (e.g., multi-VDD, power domains, UPF); Experience with complex SoC projects; familiarity with high-speed modules such as CPU, DDR, or SerDes is a strong advantage; Proficient in automation and scripting using languages such as Tcl, Perl, or Shell; Strong communication skills and a collaborative mindset, with the ability to work effectively in cross-functional teams. #J-18808-Ljbffr
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Physical Design Engineer
1 week ago
Singapur, Singapore BITSILICA PTE. LTD. Full timePhysical Design Engineer Experience: 3+ Years Salary Range: SGD Skills & Technical Expertise Required: Netlist to GDSII at block level, Subsystem Level and at Full chip. Worked on multiple tapeouts on Netlist to GDSII Hierarchical partitioning and budgeting of block-level subsystems. Implementation of high performance (HP) cores, low power designs Node...
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Physical Design Engineer
2 weeks ago
Singapur, Singapore ByteDance Full timeResponsibilities Team IntroductionThe Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop,...
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Principal Physical Design Engineer
2 weeks ago
Singapur, Singapore MaxLinear Full timePrincipal Physical Design Engineer – SoC Middle‑End (RTL2NETLIST) Responsibilities Perform design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers STA/timing closure Write low power...
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Physical Design Technical Leader/Manager
3 weeks ago
Singapur, Singapore Bitdeer (NASDAQ: BTDR) Full timePhysical Design Technical Leader/Manager Join to apply for the Physical Design Technical Leader/Manager role at Bitdeer (NASDAQ: BTDR) Physical Design Technical Leader/Manager 1 day ago Be among the first 25 applicants Join to apply for the Physical Design Technical Leader/Manager role at Bitdeer (NASDAQ: BTDR) Get AI-powered advice on this job and more...
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Research Fellow
1 week ago
Singapur, Singapore Nanyang Technological University Singapore Full timeResearch Fellow (Mechanical/Environmental/Civil Engineering/Chemistry/Physics/Materials) Join to apply for the Research Fellow (Mechanical/Environmental/Civil Engineering/Chemistry/Physics/Materials) role at Nanyang Technological University Singapore . The School of Mechanical & Aerospace Engineering (MAE) invites applications for a Research Fellow position...
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Foundation IP Senior Design Engineer
3 weeks ago
Singapur, Singapore Broadcom Full timeFoundation IP Design Engineer Overview We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have...
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Foundation IP Staff Design Engineer
3 weeks ago
Singapur, Singapore Broadcom Full timeFoundation IP Staff Design Engineer We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple...
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Principal Memory Circuit Design Engineer
3 weeks ago
Singapur, Singapore Broadcom Full timePrincipal Memory Circuit Design Engineer Join to apply for the Principal Memory Circuit Design Engineer role at Broadcom . Job Description We are seeking energetic and passionate design engineers to join our Central Engineering Group. Be part of an elite team responsible for developing foundation IP for AI products, including memory compilers, logic cells,...
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Head of Design, Platform
3 weeks ago
Singapur, Singapore UX and Design Full timeGet to Know the Team You will join the senior leadership team at Grab Design, you will work with veteran design leaders and Product, Analytics, and Engineering teams across all vertical product teams. Our mission is to create world-class, user-centric experiences that connect consumers with entrepreneurs across the region. We are dedicated to understanding...
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Principal Memory Circuit Design Engineer
3 weeks ago
Singapur, Singapore Broadcom Full timeOverview Foundation IP Principal Memory Circuit Design Engineer We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process...