Senior RTL Design Engineer

Responsibilities Contribute to IP selection and architecture definition; create functional specifications. Perform PPA evaluation and optimization. Develop RTL for functional blocks/units with architectural features and timing constraints, targeting synthesis and APR Support debugging across RTL simulation, gate-level, and post-layout simulations. Conduct...

NSING Technologies – Principal Design Engineer (Singapore) NSING (Singapore) was founded in 2018 and brings high-performance semiconductor products and solutions to the global semiconductor industry. Our product portfolio includes general and secure microcontroller units (MCU), secure integrated circuits (IC) for TPM (Trusted Platform Module), Bluetooth...

2 days ago Be among the first 25 applicants Get AI-powered advice on this job and more exclusive features. NSING (Singapore) was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products include General and Secure MCU, Secure IC for TPM (Trusted Platform Module), Bluetooth Low...

About the Role We are looking for a skilled Senior IC Designer to join our growing team. You will be responsible for driving the full digital circuit physical implementation flow (RTL to GDSII), focusing on performance, power, and area (PPA) optimization, signoff, and tape-out of advanced semiconductor products. Key Responsibilities Execute end-to-end...

JOB DESCRIPTION · Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; · Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan...

Responsibilities Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution...

Responsibilities: Develop design requirements of an NPU given system level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU. Understanding the mathematics of different convolution operators...

JOB DESCRIPTION Discussion with system engineers on SoC architecture and feedback on optimization. Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc; Discussion with synthesis engineer and back-end engineer on design optimization.    SoC DFT support; SoC verification plan and...

Overview Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts to...

Overview You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You would be joining the team to explore, evaluate and define innovative design SoC architectures, to meet or exceed the technical requirements of the...