Principal Design Engineer

2 weeks ago

Singapur, Singapore NSING Technologies Pte Full time

NSING Technologies – Principal Design Engineer (Singapore) NSING (Singapore) was founded in 2018 and brings high-performance semiconductor products and solutions to the global semiconductor industry. Our product portfolio includes general and secure microcontroller units (MCU), secure integrated circuits (IC) for TPM (Trusted Platform Module), Bluetooth Low Energy (BLE), and battery management systems (BMS). Your Role You will play a key role in the front-end SoC development team, contributing to the architecture, RTL design, and integration of high-performance microcontroller SoCs. You will drive design quality, efficiency, and technical innovation while collaborating closely with cross-functional teams including verification, physical design, firmware, and system architects. You will also mentor junior engineers and help shape best design practices within the team. Responsibilities Collaborate with SoC architects to interpret specifications and convert them into implementable designs. Lead RTL microarchitecture definition and implementation for key SoC modules and subsystems. Develop design documentation including microarchitecture specifications and interface definitions. Design, code, and integrate high-quality RTL. Perform design optimization for low power, area efficiency, and timing closure. Drive linting, CDC analysis, synthesis, and static timing checks to ensure sign-off quality RTL. Participate in RTL integration, resolving interface and system-level issues. Work closely with verification teams to define verification strategies and resolve design issues. Contribute to continuous improvement of design methodologies and reusable design components. Provide technical guidance and mentorship to junior RTL engineers. Qualifications Education: Bachelors or Master’s Degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 8+ years of hands‑on experience in RTL design for ASIC or SoC development. Technical skills: Strong expertise in Verilog RTL design (VHDL exposure is a plus); deep understanding of digital design fundamentals, SoC architecture, and microarchitecture; familiarity with AMBA bus protocols (AXI, AHB, APB); strong understanding of synthesis constraints, timing analysis, and power optimization; hands‑on experience with EDA tools such as Synopsys VCS, Verdi, Design Compiler. Other skills: Strong analytical and problem‑solving skills; ownership of design deliverables; excellent communication and teamwork skills; demonstrated leadership through mentoring or project coordination; self‑driven, adaptable, and able to manage multiple priorities in a fast‑paced environment. Preferred experiences: Lead chip top‑level design to tapeout; hands‑on synthesis and timing analysis; FPGA prototyping and hardware validation; ARM‑based MCU experience; integration of memory and peripheral interfaces such as SRAM, SDRAM, QSPI, SPI, I2C, PWM, CAN, SDMMC, Ethernet; leading or guiding junior engineers. Seniority level Mid‑Senior level Employment type Full‑time Job function Engineering and Information Technology Industries Semiconductor Manufacturing #J-18808-Ljbffr

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