Staff / Senior Physical Design Engineer (IC Backend)

We are a chip design company invested by an international consortium and founded by a senior chip design technical team. The company is headquartered in Singapore and will take root in Singapore for long-term development. The company has strong R&D capabilities and its core technical team members all have more than 10 years of experience in chip design. We...

Responsibilities Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing; Drive timing closure, formal verification, low-power analysis, and power optimization; Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD checks;...

A leading chip design company in Singapore is seeking a Digital Backend Engineer with at least 5 years of experience in physical design tasks. The successful candidate will be involved in the entire design process from Netlist to GDSII, including verification and power analysis. Strong skills in scripting languages such as TCL, Perl, or Python are...

A chip design company based in Singapore is seeking a skilled engineer to handle physical design tasks, including chip floorplan and clock architecture. Ideal candidates should have at least 5 years of experience in digital backend design, along with strong communication skills and teamwork spirit. Familiarity with scripting in TCL, Perl, or Python is a...

JOB DESCRIPTION RTL-level digital design and problem solving Function verification and support Work closely with backend team on Digital synthesis, place‑and‑route, Design for Test and Static timing analysis Lead and guide junior engineers Digital functional verification and FPGA verification JOB REQUIREMENTS Bachelor/Masters in Electronics/Electrical...

Job Responsibilities: Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers STA/timing closure Write Low power intent file (CPF/UPF) from specification and verifying...

Direct message the job poster from Canaan Inc. Regional HRBP | IHRP Certified Professional | Msc in Human Capital Leadership SMU | Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. Close the design to meet...

Key Responsibilities: IC Development Assist management team in IC roadmap and product definition specification. Manage a team of IC designers with responsibility to bring design to production. Perform feasibility studies of new project including cost and schedule estimation. Perform as project manager to lead project execution. Lead IC team to perform design...

Direct message the job poster from BITMAIN Human Resources Specialist @ Bitmain | MBA, International Recruitment Responsibility Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full‑chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; Develop,...

Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...