Physical Design Engineer
3 weeks ago
Responsibilities Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing; Drive timing closure, formal verification, low-power analysis, and power optimization; Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD checks; Support cross-functional integration and validation between frontend and backend design teams; Contribute to the development and refinement of backend flows for advanced process technologies. Qualifications Master’s degree or higher in Microelectronics, IC Design, Electrical Engineering, Computer Engineering, or a related field; 5–10+ years of hands‑on experience in digital backend design for ASIC or SoC products; Proven experience with advanced technology nodes such as 3 nm, 4 nm, or 6 nm, with successful tape‑out records; Strong background working with major foundries such as TSMC or Samsung at either block‑level or full‑chip scale; Proficient with industry‑standard EDA tools, including Cadence and/or Synopsys platforms for P&R, STA, and physical verification; Deep expertise across the full backend flow—from netlist to GDSII—including floorplanning, power planning, placement, optimization, CTS, routing, ECO implementation, RC/SPEF extraction, and STA sign‑off; Solid grasp of static timing analysis and low‑power design techniques (e.g., multi‑VDD, power domains, UPF); Experience with complex SoC projects; familiarity with high‑speed modules such as CPU, DDR, or SerDes is a strong advantage; Proficient in automation and scripting using languages such as Tcl, Perl, or Shell; Strong communication skills and a collaborative mindset, with the ability to work effectively in cross‑functional teams. #J-18808-Ljbffr
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Physical Design Engineer
3 weeks ago
Singapur, Singapore Canaan Inc. Full timeDirect message the job poster from Canaan Inc. Regional HRBP | IHRP Certified Professional | Msc in Human Capital Leadership SMU | Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS and routing. Close the design to meet...
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Physical Design Engineer
4 days ago
Singapur, Singapore BITMAIN Full timeDirect message the job poster from BITMAIN Human Resources Specialist @ Bitmain | MBA, International Recruitment Responsibility Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full‑chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; Develop,...
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Staff Physical Design Engineer
3 weeks ago
Singapur, Singapore XILINX ASIA PACIFIC PTE. LTD. Full timeTHE ROLE: The focus of this role is to plan, build, and execute the physical design of new and existing features for AMD’s IP, resulting in quality database for the final deliveries. THE PERSON: You have a passion for modern, complex physical design aspects of digital design. You are a team player who has excellent communication skills and experience...
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Staff Physical Design Engineer
4 days ago
Singapur, Singapore Advanced Micro Devices Full timeWHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...
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Principal Physical Design Engineer
3 weeks ago
Singapur, Singapore AMBITION GROUP SINGAPORE PTE. LTD. Full timeWhat You’ll Do Use Synopsys/Cadence tools to synthesize designs from RTL tonetlist. Create timing constraints for functional and test modes, workingclosely with design and DFT teams. Perform Static Timing Analysis (STA) and achieve timing closure. Write low-power intent files (CPF/UPF) and verify them usingCLP/VCLP. Run logic equivalence checks to ensure...
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Principal Physical Design Engineer
3 weeks ago
Singapur, Singapore YOXIA PTE. LTD. Full timeCreate timing constraints for functional and test modes, working closely with design and DFT teams. Perform Static Timing Analysis (STA) and achieve timing closure. Write low-power intent files (CPF/UPF) and verify them using CLP/VCLP. Run logic equivalence checks to ensure correctness. Collaborate with physical design engineers to fix netlist and timing...
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Physical Design Engineer
3 weeks ago
Singapur, Singapore ByteDance Full timeTeam Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and...
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Snr Staff Physical Design Engineer
3 weeks ago
Singapur, Singapore ADVANCED MICRO DEVICES (SINGAPORE) PTE LTD Full timeWHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...
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Physical Design Engineer: RTL-to-GDSII
3 weeks ago
Singapur, Singapore Canaan Inc. Full timeA leading semiconductor manufacturing company in Singapore is seeking a Physical Design Engineer with at least 3 years of hands-on experience in digital-physical design. This role requires a Master's or Bachelor's degree in Electrical Engineering, proficiency in Synopsys tools, and good communication skills. Responsibilities include block-level...
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Senior SoC Physical Design Engineer
3 weeks ago
Singapur, Singapore SILICON LABORATORIES INTERNATIONAL PTE. LTD. Full timeA technology firm in Singapore is seeking a highly skilled Design Engineer to join its Silicon Engineering team. This role focuses on the design and optimization of SoCs utilizing advanced methodologies. The ideal candidate will possess 4+ years of experience in ASIC physical design and expertise in EDA tools such as Synopsys and Cadence. Benefits include an...