Design Verification Engineer
2 weeks ago
Responsibilities Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels. Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out. Collaborate with design engineers to troubleshoot and resolve simulation issues. Provide support to test engineers during post-silicon validation. Mentor and guide team members and junior engineers, aiming to enhance verification efficiency. Requirements Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience. Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology. Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs. Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores. Experience in verifying designs at RTL and post-P&R gate levels. How to Apply Interested candidates, please submit your resume by clicking on “Quick Apply” or contact for more details. Please provide following information in the resume for immediate processing 1) Reasons for leaving current and/or last employment 2) Last drawn and/or current salary 3) Expected salary 4) Date of availability and/or Notice Period All applications will be treated in strictest confidence and only shortlisted candidates will be notified Wee Wai Dan EA License No : 03C5391 EA Reg No : R #J-18808-Ljbffr
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(Sr./Staff) Design Verification Engineer
2 weeks ago
Singapur, Singapore OMNIVISION Full timeDescription: As a design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. The goal is...
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Singapur, Singapore Realtek Singapore Private Limited Full timeOverview Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts to...
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Singapur, Singapore Realtek Full timeResponsibilities Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape‑out. Write...
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Design Verification Engineer
2 weeks ago
Singapur, Singapore HKM HR MANAGEMENT PTE. LTD. Full timeResponsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance. Develop reusable testbenches, test cases using constrained-random and...
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Semiconductor Design Verification Engineer
2 weeks ago
Singapur, Singapore Realtek Full timeIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus, checkers,...
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Singapur, Singapore REALTEK SINGAPORE PRIVATE LIMITED Full timeJOB DESCRIPTION: Responsibility for test plans, testbench documentation and implementation. Use SystemVerilog language, SVA and UVM methodology for block level verification. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and show progress towards tape-out. Write scripts...
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Semi-Conductor Design Verification Engineer
2 weeks ago
Singapur, Singapore REALTEK SINGAPORE PRIVATE LIMITED Full timeJOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...
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Singapur, Singapore Realtek Singapore Private Limited Full timeOverview In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Responsibilities Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as...
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Singapur, Singapore Realtek Full timeIn this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus, checkers,...
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Singapur, Singapore REALTEK SINGAPORE PRIVATE LIMITED Full timeJOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus,...
