Senior DDQA NAND CMOS Reliability Engineer

5 months ago


Singapur, Singapore Micron Full time

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

JR57808 Senior DDQA NAND CMOS Reliability Engineer

Job Description:

As a Senior DDQA (Development and Design Quality Assurance) CMOS Reliability Engineer, you will be primarily responsible for developing and optimizing quality and reliability criteria related to CMOS process for the next generation of Micron's memory parts. You will be partnering with Technology Development (TD) on latest products and technologies related to CMOS Front end/interconnect module and define quality and reliability fail modes especially NUDD (New, Unique, Different, Difficult) with goal to mitigate risk and achieve product qualification milestone successfully. You will also be required to identify, diagnose, and resolve CMOS related problems by applying failure analysis, FMEA or 8D methodology. In this position, you will be working in a highly collaborative atmosphere, interacting with various groups such as Technology Development (TD), Process Integration, electrical and physical failure analysis, Product Engineering, Quality Reliability Assurance Team to develop product that meets Quality and Reliability specs and requirements.

Responsibilities include, but not limited to:

Drive new CMOS devices or modules for the future technology of NAND from Product Quality and Reliability perspective. Define & implement Reliability test methodology for validating the risk of new CMOS module for the next generation of Micron's memory parts. Provide insights and guidance to the Global Quality (GQ) management team on topics involving CMOS. Interact and collaborate with Design Team, TCAD, modeling, and layout teams to drive clearer definition of CMOS device and reliability improvements across multiple tech-nodes and designs. Develop/re-define inline and electrical critical specifications criteria for optimum product performance and drive activities to get them to manufacturing process capability. Characterize and validate new CMOS device, models, and test structures for developing future NAND products. Develop, establish new CMOS Param or optimize scribe design for CMOS parameters. Collaborate with various stakeholders and provide DDQA independent assessment on Quality & Reliability items in various technology development milestones (EPP, SVC, MSC, VME), escalate issues and collaborate for timely risk mitigation and resources, also provide inputs for Leaderships in making decision on passing the Qual milestone (Low Tier Qual/High Tier Qual/Auto Qual etc). Support technology transfer to production facilities (some international travel may be required). Partner with multiple stakeholders in Process Conversion Review Board Meeting (PCRB) to improve coverage from various aspects of product quality and reliability and prevent post qual escapes or excursion triggered by conversion. Identify gaps and drive initiatives/programs/business process to build margin around structural, electrical, and reliability performance. Build Product Fail Modes Repository based on NUDD (proactive) and previous issues (reactive), and work with key stakeholder to prevent issues or implement effective detections controls and containment. Deliver a new Product Fail Modes Repository and their Effective Detection Controls and Containment Document to meet technology development and Transfer timeline. Partner with Manufacturing (MFG) or Central Quality teams on current high-volume products to sustain and further develop the Product Fail Modes Repository through regular refresh meeting.

Minimum Qualifications:

4+ years’ experience in semiconductor related engineering, preferably in 300mm wafer fab. Hands-on experience on advanced CMOS engineering and reliability, specialized in Microelectronics and Semiconductor Device Physics is a requirement. Direct fab experience with nonvolatile memories manufacturing, knowledge of TCAD, K2 view layout, and NAND product are highly desirable. Understanding of Reliability items for CMOS and Array Understanding of electrical specifications, Probe and Param registers Knowledge of 3D NAND Fab processes, flow and common reliability and yield fail modes is preferred. Highly skilled at problem-solving activity and capability of leading cross functional team.  Understanding on technical risk assessment, FMEA, and 8D methodology for root cause analysis and problem solving. Effective verbal and written communication skills in English. Good multitasking skills and ability to set priorities in a fast moving, dynamic environment. Ability to work independently, with minimal direction, and a focus on meeting commitments. Real passion for improving product quality to increase customer satisfaction.

Education and Experience:

Bachelor’s degree or higher in electrical or electronics engineering, physics, chemistry, mechanical engineering, material science, or other applied engineering discipline.

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