Senior Ic Verification Engineer

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Position Summary** Perform ASIC Verification **Key Responsibilities** - Digital IC Verification - Develop and maintain verification environment for module and SOC level level using UVM methodology. - Create and...

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Key Responsibilities** Digital IC Design Verification - Perform front-end verification using UVM methodology - Work with Systems and Software engineers on FPGA verification - Lead DFT related activities - Scan...

**Responsibilities**: - Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications - Design and develop verification testbenches using industry-standard verification languages and methodologies - Write and execute test cases to verify mixed-signal circuits for functionality,...

A leading technology firm in Singapore is seeking a verification engineer to develop and review test plans for IC design. The ideal candidate will have a degree in Electrical/Electronics/Computer Engineering and at least 1 year of experience in Silicon/IP verification using SystemVerilog/UVM. Strong communication and analytical skills are essential. This...

JOB DESCRIPTION: - Perform with various activities on RTL design implementation and verification at SoC level. - Responsible for RTL coding, logical synthesis, functional test plan, test bench development, RTL and gate-level simulation/verification, code coverage, formal verification, test vector generation and design documentation. - Work and provide high...

Department: IC Design & Development Position Summary: Key Responsibilities Perform front-end verification using UVM methodology Work with Systems and Software engineers on FPGA verification Lead DFT related activities – Scan Insertion, ATPG, Pattern Validation Work with test team in debugging production test issues Help debug & correct any functional...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...

Overview Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests for DUT...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...