Engineer / Senior Engineer / Staff Engineer - IC Design Verification

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Key Responsibilities** Digital IC Design Verification - Perform front-end verification using UVM methodology - Work with Systems and Software engineers on FPGA verification - Lead DFT related activities - Scan...

**Responsibilities**: - Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications - Design and develop verification testbenches using industry-standard verification languages and methodologies - Write and execute test cases to verify mixed-signal circuits for functionality,...

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Position Summary** Perform ASIC Verification **Key Responsibilities** - Digital IC Verification - Develop and maintain verification environment for module and SOC level level using UVM methodology. - Create and...

**Your new company** Looking for a IC Design engineer role with a listed company that engages in the manufacture and distribution of electrical/ electronics components in Singapore. **Your new role** - The Senior Mixed-Signal IC (MEMS Interface) Design Engineer will be responsible for the design and development of capacitive and/or piezoelectric MEMS...

**Department**: IC Design & Development - **Reporting To**: Manager - IC Design & Development - **Location**: Singapore - **Position Summary**: **Key Responsibilities** Digital IC Design - Perform Verilog RTL design to meet product specifications and requirements - Perform Logic Synthesis, Static Timing Analysis - Work with Physical designer to achieve...

JOB DESCRIPTION: - Perform with various activities on RTL design implementation and verification at SoC level. - Responsible for RTL coding, logical synthesis, functional test plan, test bench development, RTL and gate-level simulation/verification, code coverage, formal verification, test vector generation and design documentation. - Work and provide high...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...

Company Allinton Engineer & Trading Pte Ltd Designation IT Engineer Date Listed 27 Oct 2025 Job Type Entry Level / Junior Executive - Intern/TS Job Period Immediate Start, For At Least 3 Months Profession IT / Information Technology Industry Computer and IT Location Name 331 Jalan Besar, Singapore Address 331 Jln Besar, Singapore...

Overview Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests for DUT...

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests...