Dft Design Engineer/dft设计工程师

职位名称 AI工程师 公司简介...

Description Position Overview We are seeking a highly skilled and experienced Senior/Staff DFT (Design for Test) Engineer to join our team. In this role, you will be instrumental in defining and implementing the test strategy for our complex CIS/SoC/TDDI designs. You will take ownership of the entire DFT flow, from architecture to pattern generation,...

Job Overview:We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive...

**Job Description**: - Design/verification for Clock/JTAG/Analog/DFT IP - Scan Insertion, ATPG, scan verification and pattern generation - Memory BIST insertion, validation and pattern generation - Analysis of Functional Design for Testability, including product functionality and access through external connections, BIST and Board Level Diagnostics, control...

Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra -low power SoC based on subthreshold operation using standard EDA tools.Develop and implement low -power DFT architecture and infrastructure.Generate structural test vectors, analyse, and improve coverage, test time and test cost.Perform pre/post -layout scan and MBIST simulations.Work with...

Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis - Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results - Research and evaluate state-of-the-art DFT architectures and methodologies for SoC/IP...

**Key Responsibilities**: - Work closely with design team and make sure DFT structures are correctly inserted. - Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs. - Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model -...

Responsible for scan insertion, MBIST, ATPG for SOC based design using industry standard EDA tools.Generate test vectors, analyze and improve test coverage, reduce test time and test cost.Perform pre/post-layout scan and MBIST simulations.Work with designers on STA, physical, power and logical issues related to DFT.Work with test engineers to bring up all...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity...

Responsibilities Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop,...