Mask Layout Design Manager

2 days ago

Tampines, Singapore Advanced Micro Devices, Inc Full time

Overview:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

**Responsibilities**:
**THE ROLE**:
The SoC Integration team is responsible for integrating various IPs and sub-blocks from design teams, verifying all physical and electrical aspects of the chip, preparing chip level layout for timing and EMIR analysis, and driving to a successful tape out.As a Manager Mask Layout Design on the SoC Physical Integration team, you'll work with various groups, including Design, CAD, and process technology teams, while performing various tasks to ensure high quality and seamless chip level integration on the road to tape out FPGAs/ACAP devices.

**THE PERSON**:
**KEY RESPONSIBILITIES**:

- Managing/Leading a team of mask layout designers
- Executing flows and methodologies for chip level integration
- Chip level integration, including bump/ubump planning, physical verification, and electrical verification
- Layout of sub-cells/leaf cells that are needed to build IP/macro using CAD tools to integrate at top level
- Creating/Presenting schedules and status reports
- Coordinating/Communicating with design teams, CAD, and process technology teams across geographies

**JOB REQUIREMENTS**:

- At least six (6+) years of layout design experience in lower process nodes
- Management experience preferred but not required
- Good understanding of reliability concepts and layout electrical parameters/closure
- Hands-on experience using Cadence and Mentor tools or equivalent
- Strong debug capabilities with parasitic extraction, LVS/DRC, and other physical/electrical verification checks
- Familiarity with circuit design concepts/flows and IC manufacturing processes
- Understanding of parasitic impact on circuit performance and/or digital SoC flow is a plus
- Scripting skills is a plus (Perl, Python, Tcl, etc )
- Ability to work across functions, levels, and remote sites
- Ability to work outside of official working hours, if assigned, to support remote design teams
- Outstanding communication skills and teamwork

**ACADEMIC CREDENTIALS**:

- Bachelor’s in Electrical Engineering is required
- Master’s in Electrical Engineering is preferred
- Any certification course(s) in VLSI custom layout field will be an added advantage

**LOCATION**:
Singapore

LI-JV1

Qualifications:

- Benefits offered are described: _AMD benefits at a glance
_._

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