Memory Layout Engineer

22 hours ago

Fusionopolis Walk Central Singapore Uni Connect Full time $120,000 - $180,000 per year

Should have goodunderstanding of basic memory architecture, and memory leaf cell layout creation.Should have good understanding of basic CMOSand finfet circuits.Experience and familiarity in various physicalverification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR,etc.Understanding and working knowledge of goodlayout practices (matching, etc), especially in advanced process nodes, like7nm, 5nm, 3nm etc, is preferred.Good understanding of deep sub -micron and DFMissues in layout design (WPE, LOD effects, etc.).Minimum 3 years working experience in MemoryLayout Design (SRAM, EFUSE, Via -ROM, TCAM, etc.).Proficient with Synopsys Laker/CustomCompiler, or Cadence Virtuoso.Familiar with Mentor Graphics Calibre, andUnix environment. RequirementsBachelor'sDegree/Diploma in Electrical/Electronic Engineering or equivalent.Responsiblefor the development of memory layouts in advance CMOS and finfet processes.Perform physical verifications of differentmemory types, from bottom cells to top hierarchy.Undertake the assignments independently or ina team.​Work closely with memory design engineers andmemory compiler engineers to ensure highest quality memory layouts.

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