Memory Layout engineer

23 hours ago


Singapore Central Singapore Uni Connect Full time $120,000 - $180,000 per year

JobResponsibilities:·       Implement top quality of layout for memory whichmeet the specifications set forth by designers and layout leads while meetingthe project objectives and milestones.·       Layout implementation process: floor planning,layout construction, physical verification and memory compiler leaf -cellcreation.·       Diligently perform all physical& reliability verifications (DRC/LVS/ERC/etc.) on the layout designs andensure the database is fully compliant with all requirements of tape -out flow. Work closely with multi -functional members tooptimize layout realization according to the desired power, performance and areaoptimization requirementRequirementsMinimumQualifications:·       Bachelor's degree in Electrical/Electronic/Computer Engineering or equivalent·       At least 5 years of directexperience in custom Memory layout implementation (SRAM/ROM/TCAM) in advancedfinFET/GAA process nodes·       Proficient in understanding DRM ofadvanced CMOS technologies and have a good understanding of deep sub -micron and DFM issues (e.g., WPE, LODeffects, etc.)·       Strong knowledge in floor -planning techniques at different hierarchies, with emphasis on power meshplanning, critical block placement, critical signal routing and top -down integration flow·       Strong knowledge in executing and debugging various physical verification checks likeDRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.·       Proficient in Synopsys/Cadencelayout editors·       Ability in script programming (e.g.,Python, Tcl, Perl or C -shell) is aplus·       Team player and effective in cross -team communication and timemanagement


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