IC Physical Design Engineer

5 days ago

West Region, Singapore SmartHire by SEEK Full time $8,000 - $11,000 per year
Our client is seeking an IC Design Engineer - Backend Place and Route (P&R) to join their team
About Our Client

Our client is a leading provider of high-performance semiconductor products and solutions. Specializing in General and Secure Microcontroller Units (MCUs), Secure Integrated Circuits (ICs) for Trusted Platform Module, Bluetooth Low Energy (BLE), and Battery Management Systems (BMS)

What you'll be doing?
  • SoC Design Implementation: Execute complex top-level floor-planning, power plan design, and placement of IP blocks, pads, and analog blocks for cutting-edge IC designs.
  • Low Power Optimization: Implement low power layout strategies with multiple power domains, incorporating power switches and isolation cells.
  • Timing Mastery: Handle critical timing closure tasks, including setup, hold, signal integrity, and cross-talk noise management.
  • Verification Excellence: Perform physical verification (DRC, LVS) and efficiently resolve design rule violations.
  • Performance Optimization: Enhance designs for optimal power, performance, and area (PPA) using advanced EDA tools.
  • Cross-functional Collaboration: Work seamlessly with RTL design, synthesis, DFT, and packaging teams to ensure smooth integration and successful tapeouts.
  • Tool Proficiency: Utilize industry-standard tools like Cadence Innovus, Synopsys ICC2, and Mentor Calibre to drive efficient workflows.
  • Automation and Scripting: Develop and maintain automation scripts using TCL, Perl, or Python to streamline P&R processes.
  • Documentation and Reporting: Generate comprehensive reports on P&R progress, challenges, and metrics, and actively participate in design reviews.
Who are they looking for?
  • Educational Background: Candidates with a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Industry Experience: Individuals with at least 5 years of experience in IC physical design, including hands-on SoC level P&R in advanced nodes (40 nm and below).
  • Technical Expertise: Professionals with a strong background in CTS, timing closure, power grid design, pad placement, analog/digital placements, and physical verification.
  • Tool Proficiency: Candidates skilled in EDA tools such as Cadence Innovus, Synopsys ICC2, or similar platforms.
  • Design Knowledge: Individuals with a robust understanding of timing analysis (STA), clock tree synthesis, signal integrity, and low-power design techniques.
  • Scripting Skills: Familiarity with scripting languages (TCL, Perl, Python) for automation purposes.
  • Verification Knowledge: Understanding of DRC, LVS, and physical signoff methodologies.
  • Problem-Solving Abilities: Strong analytical, problem-solving, and debugging skills.
  • Communication Skills: Excellent communicators who thrive in cross-functional team environments.
  • Advanced Technology Experience: Knowledge of FinFET technology nodes and Full Depletion FDSOI with Back-bias and Forward Bias voltage technology is a plus.
  • EM/IR Expertise: Experience with EM/IR drop analysis and mitigation is advantageous.
Other Information:
  • Working Hours: Monday to Friday
  • Location: Science Park Rd, Teletech Park, Singapore 117674
  • Salary: $8000 - $11000
How to apply

Ready to join this role? Click Apply now to submit your resume and share your availability and expected salary with us

We encourage all qualified individuals to apply, regardless of background or experience level. Your unique perspective could be exactly what we're looking for

All information received will be kept strictly confidential and will be used only for employment-related purposes.

Jobs DB Singapore Pte Ltd | 24C2640

Low Jia Yi | R

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