Senior / Staff SerDes Digital Design

3 days ago


Singapore Uni Connect Full time $150,000 - $200,000 per year

Participate in high -level product specifications, microarchitecture and implementation of high -speed memory interfacesPerform RTL coding, LINT checking and sanity testing on implemented designsWork with the verification team for lab debuggingWork with the software team and/or customers to solve problems, debug and tune system performanceRequirementsBachelor's degree in communications, electronic engineering or computer engineering, master's degree preferredMore than 6 years (staff engineer) and 10 years (senior staff engineer) of ASIC design experience, familiar with ASIC development processGood Verilog HDL coding skills and EDA tools such as synthesis and timing analysisFamiliarity with high -speed interfaces such as DDR, SerDes, PCIe is preferredAbility to solve customer problems and deliver results in a timely mannerStrong organizational and communication skills where English is a must and Chinese is preferred



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