DV Manager

2 days ago

Science Park North West Singapore Uni Connect Full time $180,000 - $220,000 per year

Job Description: Lead and contribute to a high -performing team responsible for creating state -of -the -art Secure Low Power SoC ARM -based MCU solutions, spanning low -end to high -end performance in a dynamic IC design environment.Responsibilities:Provide technical leadership in developing UVM -based test suites and simulation environments for verifying both standalone IP and complex SoC ARM -based systems integrating diverse digital and analog IPs.Design, build, and review Verification IPs from industry -standard specifications, ensuring best -in -class implementation.Oversee the implementation of comprehensive test cases derived from product and industry standards, utilizing constraint -random and directed methodologies to maximize verification coverage.Drive the development of test environments and creation of test cases for multi -power domain SoC architectures, incorporating UPF inputs to rigorously verify all functional features within each domain.Document, compile, and correlate verification results to ensure full functional compliance with specification requirements.Guide gate -level netlist simulation and debug for all process corners, collaborating closely with back -end teams to achieve timing closure prior to tape -out.Mentor, lead, and support verification engineers, conducting regular design and code reviews, and fostering continuous improvement in functional and code coverage.Coordinate with IP design teams to proactively identify and resolve functional issues and optimize verification processes.Requirements:BSc, MSc, or PhD in Electrical/Electronic or Computer Engineering.Minimum 5 years of hands -on experience developing advanced UVM/OVM/VMM test suites.Expertise in state -of -the -art verification techniques, including assertion - and metric -driven methodologies, within UVM environments.Proficiency in SystemVerilog, C++, C, SystemC, and/or Verilog.Demonstrated experience in multi -power domain verification, including writing CPF/UPF.Hands -on experience with formal verification tools such as Synopsys VCS or Cadence IES.Strong verification experience with ARM -based CPU Cores and major interface protocols (SPI, I2C, UART, USB, PCIe, etc.) and transceivers.Proven ability to lead, mentor, and guide junior engineers, fostering team excellence and skill development.Self -driven, able to work independently and collaboratively, with a strong commitment to delivering results on schedule.Excellent written and verbal communication skills.

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