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Layout Engineer
2 weeks ago
JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption.
Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for talents to join our journey for rapid growth.
**What will you be working on**:
1. In this role, you will work with our analog design engineers to layout the high speed, high performance analog circuit such as: high speed and low power ADC, high linearity and low noise amplifier, high linearity and low noise analog filter; high performance PLL, low noise OSC, high speed SERDES, inductive or capacitive base power converter, low noise LDO, high performance temperature sensor, low noise and high accuracy voltage/current reference, IO and ESD cells and etc.
2. Engage in floor planning, die size estimates, block level routing and top level chip assembly.
4. Demonstrate your experience with analog layout for silicon chips in mass production.
5. Read and interpret Design Rule Manuals.
6. Perform physical layout implementation at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation.
**What are we looking for:
1. BS in Electrical engineering or equivalent, 5 years or more of CMOS analog circuit layout experience.
2. Ability to layout analog circuitry in a size/time-constrained environment.
3. Understand how to optimize layout to reduce parasitic effect in high speed analog circuit.
4. Understand device matching techniques such as common centroid, matching, and the use of dummy devices, etc.
5. Understand signal conditioning/protection techniques such as shielding, isolation, etc.
6. Understand ESD and Latch-up issues and have experience in good layout practice to prevent ESD and Latch-up issues.
7. Ability to solve design problems while using a combination of technical skills, intuition, and creativity.
8. Proficiency in floor planning activities with block level and top level assembly/routing.
9. LVS troubleshooting and debugging skills.
10. Excellent collaboration skills including written and verbal communication.
11. Much have layout Experience in 28nm or 40nm and experience in FinFET is preferred.
