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Active Requirement

2 weeks ago

Singapore Vhunt4u Full time

**Work Location** : Singapore

**Work Expertise** : 5+ years

**Desired Profile**:

- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- Expertise in ASIC / SOC verification.
- Expertise in UVM, System Verilog and constrained random testing.
- Expertise in testbench architecture and SOC-level verification strategies.
- Expertise with protocols such as AXI, AHB, APB, PCIe, USB, or DDR.
- Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Familiar with waveform debugging tools such as Verdi or DVE.
- Working knowledge of low-power verification (UPF) and DFT / scan concepts.
- Knowledge of scripting languages (Python, Perl, TCL) for automation.
- Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals.
- _VISA SPONSORED_

**Job Specs**:

- Develop and maintain full-chip verification environments using SystemVerilog UVM methodology.
- Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE).
- Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features.
- Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level.
- Perform debugging, waveform analysis, and triage of failures in RTL simulations.
- Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied.
- Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues.
- Participate in formal verification, assertion-based verification, and low-power simulations.
- Support regression testing, issue tracking, and coverage closure.