Memory Modeling Engineer

2 weeks ago


Singapore 聯發科技 Full time

[What you bring] - Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related discipline with at least 3 years of semiconductor industry experience. - Have at least 3 years experience using Linux systems. - Good understanding of Verilog syntax and its various aspects, such as behavioral, RTL and synthesizable Verilog is a must. - Good understanding of liberty timing syntax. - Good understanding of upf and system Verilog. - Knowledge and experience with EDA simulation tools such as VCS, NC is required. - Experience with EDA tools will be helpful: 1.DFT: Logicvision, Tessent, Fastscan 2.Synthesis: Design compiler, Genus 3.Simulation tools: VCS, QuestaSim, NC 4.STA tools such as PrimeTime - Good scripting and flow automation skills, in Perl or Python. - A team player, meticulous, able to work and learn independently are important attributes for this job. Location: One North, Singapore



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