Physical Scientist

**Duties**:
Serves as a CHIPS R&D program manager, for one of the Programs in the CHIPS R&D Office. These programs include the National Advanced Packaging Manufacturing Program (NAPMP), the National Semiconductor Technology Center (NSTC), Integration and Policy Office, or Semiconductor Manufacturing Coordination Office and one or more Manufacturing-USA Institutes (MFG-USA). The NAPMP will strengthen semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem. The NSTC will conduct research and prototyping of advanced semiconductor technology and grow the domestic semiconductor workforce to strengthen the economic competitiveness and security of the domestic supply chain. The Integration and Policy Office will ensure effective coordinated execution of CHIPS research programs with other CHIPS programs and other government programs. The Semiconductor Manufacturing Coordination Office will align CHIPS research programs with Manufacturing USA program research on (1) the virtualization and automation of maintenance of semiconductor machinery, and (2) development of new advanced test, assembly and packaging capabilities.

As program manager for each of these programs, the applicant will:

- Provide visionary leadership across diverse and evolving technical domains
- Exhibit strategic thinking, innovation, and high-level technical leadership.
- Lead significant contributions to semiconductor technologies driving organizational and industry advancements.
- Determine key performance indicators, assess risks, and ensure long-term programmatic success.
- Manage complex semiconductor and related technology projects.
- Convene stakeholders inside and outside the CHIPS R&D program, including academia, non-profits, industry associations, and small businesses to advance the CHIPS R&D Office strategy.

**Requirements**:
**Conditions of Employment**:

- U.S. citizenship
- Males born after 12-31-59 must be registered for Selective Service
- Suitable for Federal employment
- Completion of Confidential Financial Disclosure, Form OGE-450
- Bargaining Unit Position: No

**Qualifications**:
**Basic Requirements**:
**A**. Degree: physical science, engineering, or mathematics that included 24 semester hours in physical science and/or related engineering science such as mechanics, dynamics, properties of materials, and electronics.
- **OR**
***
**B.** Combination of education and experience - education equivalent to one of the majors shown in A above that included at least 24 semester hours in physical science and/or related engineering science, plus appropriate experience or additional education.
- **In addition to the above basic requirements**:Applicants must have one year of specialized experience equivalent to at least the GS-14 level (ZP-IV at NIST) in the federal service. Specialized experience is defined as experience in:

- Leading efforts to create and implement semiconductor EDA technology solutions tailored to challenges in advanced packaging, multi-chip design, design-technology co-optimization, systems-on-chip design-for-test/reliability/manufacturability, emerging memory technologies, and secure design and integration for the IoT.
- Leading efforts to create and implement semiconductor technology solutions including co-optimization techniques for performance and power management, radiation hardening, power-efficiency and fault-tolerance.
- The qualification requirements in this vacancy announcement are based on the U.S. Office of Personnel Management (OPM) Qualification Standards Handbook.
- Applicant Reconsideration

**Education**:
**Additional information**:
This position is covered under NIST's Alternative Personnel Management System (APMS). The APMS is a pay-for-performance system with excellent HR flexibilities to help NIST recruit and retain top talent. Find out more about the APMS here
- Click all links in this vacancy announcement to view additional information or instructions.
- All documents submitted for this announcement must be legible in order to make qualification or eligibility determinations.
- A trial period may be required.

This position requires the filing of an OGE-450 Confidential Financial Disclosure Report within 30 days of onboarding and annually thereafter.- NIST strives to build a flexible and encouraging work environment to bring out the best in our employees. To help our employees balance responsibilities at home and at work, NIST offers a variety of work-life flexibilities such as:

- Telework
- Flexible work schedules
- Paid parental leave
- Paid vacation
- Sick leave
- Family-friendly leave
- Childcare subsidy program for qualifying families
- Child and elder-care resources
- On-site childcare center
- Lactation spaces
- Wellness programs
- Fitness center
- Employee assistance programs
- Benefits

A career with the U.S. government provides employees with a comprehensive benefits package. As a federal employee, you and your family will have access to a range