R&d Engineer Senior Ic Verification
3 days ago
Responsibilities include:
- Actively understand Design under Test (DUT);
- Define and peer-review test plan;
- Write test patterns as per defined test plan;
- Execute test patterns, actively debugging RTL simulation issues;
- Execute regression of test patterns;
- Collect and actively improve RTL code coverage;
- Document test patterns, and write sign off report;
- Provide help and guidance to junior members in team;
**Required **qualifications:
- Bachelor or Master degree, majoring Electrical or Computer Engineering;
- 3~5 years working experiences as either Designer or Verification Engineer;
- Experienced with logic design, using hardware description language Verilog or SystemVerilog;
- Experienced with UVM;
- Experienced with RTL simulation and debugging, using tools from any of the following vendors: Synopsys, Cadence, or Mentor;
- Experienced with Linux scripting (eg, Bash, C Shell, Perl, or Python)
- Good English communication skills;
- Basic knowledge of version control system (SVN for example);
- Self-motivated, self-disciplined and responsible;
Possessing any of the following will be advantage:
- Experienced with ARM CPU based digital system;
- Experienced with C programming;
- Experienced with low power simulation, using UPF;
- Experienced with gate level simulation;
- Experienced with design prototyping using FPGAs;
- Able to speak or read Chinese language;
**Job Types**: Full-time, Part-time, Permanent, Contract, Internship, Student job
Contract length: 24 months
Part-time hours: 10 per week
**Salary**: From $8,000.00 per month
**Benefits**:
- Additional leave
- Professional development
- Work from home
Schedule:
- Flexible hours
- Monday to Friday
Supplemental pay types:
- 13th month salary
- Performance bonus
- Yearly bonus
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