Senior Design Verification Engineer

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About the team

The Digital Subsystems team is responsible for the research and development of digital architectures and IPs from concept to production. We develop compute engines (AI/ML), processors (RISC-V), accelerators, peripherals and system IP. Our activities include advanced research & development, high-level modeling, architecture, RTL design, timing/power/area optimization, formal and UVM verification within an automated framework. We value innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team.

Design Verification Technical Lead

The Verification Lead will be responsible for technical leadership, direction-setting and significant hands-on contribution of advanced digital verification projects. The lead will have direct responsibility for the planning and execution of methodology and flows to be employed in the execution of verification projects. The lead will directly supervise the technical activities of verification projects such as test planning, execution, and reviews at both IP and system-levels. Included is communicating and synchronizing methodology and test development with verification leads and engineers at other sites. The lead is also expected to provide technical coaching and mentoring to team members on verification approaches, languages, and tools/methodologies.

**Responsibilities**:

- Provide technical leadership for a team of verification engineers
- Generate and execute verification plan based on specifications
- Architect and implement testbenches using UVM-based constrained-random
- Utilize architectural models to verify functionality of digital IP
- Develop integration and reuse guidelines for IP integration
- Coverage definition, implementation, and analysis
- Mentor junior engineers
- Support IC teams in integration and use of IPs
- Develop and improve flows and methodologies for efficient and high-quality development
- Skill development and training on modern verification techniques such as formal

Required Experience & Skills:

- Technical Team leadership and project execution ownership
- Ability to plan, track and manage a complex verification project comprising of a team of engineers
- Ability to mitigate unforeseen obstacles and maintain on-time execution to meet project schedules
- Technical leadership and mentorship
- Extensive experience with implementation of UVM testbenches:

- Verification component design with emphasis on decoupled stimulus and checking, robust random stimulus generation and reuse
- Reuse of IP-level testbenches in subsystem and system-level verification
- Assertion-based verification
- Ability to define and specify requirements for verification-related flows including:

- Simulation control and coverage
- Regression deployment and coverage collection
- Experience with EDA simulation tools

Preferred Experience & Skills (any of the below):

- Experience in deploying and maintain formal property verification at an IP-level for interface protocol and internal functional verification.
- Experience in developing and deploying executable and reusable test plans and tracking their closure through regression
- Experience in verification of microprocessors
- Developing and debugging assertions with formal property verification for interface verification and/or internal processor operation
- Experience with processor debug techniques and design including test interfaces, debug and trace implementation and general debug infrastructure
- Experience developing and maintaining software toolchain and infrastructure to facilitate software testing of processor implementations