Semiconductor Senior Design Verification Engineer
3 days ago
In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition. Responsibilities Develop detailed module level and SoC level test plans for all the functional features, based on the design spec. Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards. Develop directed and constrain-random verification functional tests and simulate using EDA tools to verify functional spec is working. Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features. Collaborate with digital design team to debug functional testcases and deliver functionally correct designs. The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Qualifications Bachelor/Masters in Electronics/Electrical Engineering. Level of Expertise: At least 6+ year of SOC/IP verification skills. Strong communication, analytical and documentation skills and ability to interface with other groups. Strong VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products. Strong hardware functional verification language and Object-oriented language development skill. Preferred with strong knowledge in System Verilog, UVM, Python (TCL/Perl a plus) Familiar with ASIC verification methodology, tools, and development flow. Preferred Working experience: Ethernet L2/L3 switch/router, SOC, AMBA bus, high-speed IO (USB-2/3/4, PCIe gen2/3/4/5, MIPI CSI-2/DSI-2 and SATA), Flash controller, or CPU peripherals, AMBA bus and SOC system controller. Additional Working experience as plus: Automotive or IOT or Video. #J-18808-Ljbffr
-
(Sr./Staff) Design Verification Engineer
2 weeks ago
Singapore OMNIVISION Full timeJob Title (Sr./Staff) Design Verification Engineer at OMNIVISION Description As a design verification engineer, you will be part of a passionate verification team that develops and deploys state-of-the-art verification methodologies for complex designs. Your goal is to achieve zero-defect verification using advanced techniques such as UVM, C/C++...
-
Design Verification Manager
2 weeks ago
Singapore OMNIVISION Full timeResponsibilities Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically...
-
Design Verification Engineer
1 week ago
Singapore NUWAY CFR PTE. LTD. Full time $90,000 - $120,000 per yearOne of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Engineer (DV)Location : SingaporeExperience : 3 to 7 years.Technical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso...
-
Design Verification Engineer
2 days ago
Singapore Ambiq Full time**Company Overview**: Ambiq has been on a singular mission since 2010 to put intelligence everywhere by creating the most energy-efficient semiconductor solutions for IoT endpoint devices. Using the revolutionary Subthreshold Power Optimized Technology (SPOT®) Platform, Ambiq's record-breaking ultra-low power solutions, including MCU and SoCs, have helped...
-
Senior Engineer, Design Verification
4 days ago
Singapore Marvell Full timeAbout Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire...
-
Digital IC Verification, Graduate Engineer
3 days ago
Singapore Espressif Systems Full timeResponsibilities Define verification plans and test cases based on chip design specifications, and establish the verification environment Collaborate with chip design engineers in identifying and fixing design defects and continuously improve verification coverage Participate in gate-level simulation and formal verification Optimize tools and the...
-
Senior Engineer, Design Verification
6 days ago
Singapore Marvell Full timeAbout Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire...
-
Principal Memory Circuit Design Verification
1 week ago
Singapore Micron Full time**Our vision is to transform how the world uses information to enrich life for all.** Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it...
-
Design Verification Lead
1 week ago
Singapore NUWAY CFR PTE. LTD. Full time $13,200 - $39,600 per yearOne of our US Global Semiconductor IC design is growing their design teams in Singapore.Role : Design Verification Lead (DV)Location : SingaporeExperience : 10+ yearsTechnical Requirements:o Expert-level UVM and SystemVerilog verificationo Advanced coverage-driven verification methodologieso Experience with complex SoC verification strategieso Knowledge of...
-
(Sr./Staff) Design Verification Engineer
1 week ago
Singapore OmniVision Technologies Singapore Pte. Ltd. Full timeAbout the job (Sr./Staff) Design Verification Engineer Position Overview: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to...
