Staff physical design engineer

Roles & ResponsibilitiesWe have an exciting position in the explosive growth area of Data Center Enterprise Storage. In this role you will be responsible for developing the most advanced semiconductor devices to support stringent high capacity storage needs across all the top tier service providers. Our IC R&D team is looking for an experienced physical...

Roles & ResponsibilitiesPosition Overview: We are seeking a skilled Physical Design Engineer to join our team. As a Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks,...

Roles & ResponsibilitiesWhat you will do APU Physical Design Implementation for APU partitions focus on MDLA/NDLA n5/n4/n3e/ process Physical VerificaTion to deliver clean APU partition gds N5/n4/n3e/ process Perform Timing Closure ECO for APU partition including PrimeTime timing check and twk timing ECOWhat you bring Apr hands on for n5/n4/n3e process...

Roles & ResponsibilitiesPosition Overview: We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low...

Roles & ResponsibilitiesJob Description: Collaborate with the front-end design team to finalize chip floorplan, clock architecture, and power plan. Lead physical design tasks from Netlist to GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability, and tapeout. Research physical...

Roles & ResponsibilitiesJob Responsibilities: Advanced low-power physical design/integration flow development. Full-chip floor planning and place & route. Power network design and analysis. Support signoff timing closure, power integrity, and signal integrity. Physical Verification using DRC, LVS.Requirements: Bachelor's degree or above in Electronics,...

Job Description:We are seeking a skilled Senior Physical Design Engineer to join our team at JONDAVIDSON PTE. LTD. As a key member of our digital backend design team, you will be responsible for completing the chip floorplan, clock architecture, and power plan. Your tasks will include physical design from Netlist to GDS2, including P&R, formal verification,...

Roles & Responsibilities We are a chip design service company invested by an international consortium and founded by a senior chip design technical team. The company is headquartered in Singapore and will take root in Singapore for long-term development. In the future, we will also open branches in China, Japan and other places. The company has strong R&D...

Roles & ResponsibilitiesJob Description：1. Works with the front-end design team to complete the chip floorplan , clockarchitecture, and powerplan .2. Takes charge of the physical design tasks from the Netlist to the GDS2, including P&R,formal verification, static timing analysis, physical verification, power analysis, design forreliability (DFR) and...

Roles & Responsibilities Responsible for the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape out. Liaise with the front-end design team to complete the chip floorplan, clock architecture, and power plan. Study the...

Job Title: Senior Physical Design EngineerWe are working with NodeFlair to find a Senior Physical Design Engineer (Backend) to join their Singapore team.The compensation package is competitive at SGD 84k - 126k per year, excluding bonus.Key Responsibilities:Collaborate with the front-end team to finalize chip floorplan, clock architecture, and power...

We are working with a design company, and as part of their continued growth, Node Flair has been engaged to search for Senior Physical Design Engineer (Backend) to join their Singapore team. The package is competitive at SGD 84k - 126k / year (excluding bonus). Job Description: Collaborate with the front-end team to finalize chip floorplan, clock...

Foundation IP Staff Design Engineer Location: Singapore-Yishun Time Type: Full time Posted On: Posted 3 Days Ago Job Requisition ID: R021277 Job Description: We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products...

Foundation IP Staff Design Engineer Apply locations Singapore-Yishun time type Full time posted on Posted 2 Days Ago job requisition id R021277 Job Description: We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products...

We are working with a design company, and as part of their continued growth, NodeFlair has been engaged to search for a Senior Physical Design Engineer (Backend) to contribute to their Singapore team.The compensation package is competitive at SGD 84k - 126k / year (excluding bonus).Key Responsibilities:Collaborate with the front-end team to finalize chip...

Roles & ResponsibilitiesJob Description Working on 6nm and below advanced process project APR and Timing/PI sign-off Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros) Take the Block or Block coordinator role for complex blocks Do early prediction for critical APR/Timing/PI issuesJob Requirements ...

Job Description: Skills and Responsibilities: Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 to 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies. Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis,...

About the Role:As a Physical Design Engineer at BITSILICA PTE. LTD., you will be responsible for designing and developing high-performance and low-power digital ICs. Your expertise in netlist to GDSII conversion, hierarchical partitioning, and budgeting of block-level subsystems will be invaluable to our team.Key Responsibilities:• Netlist to GDSII at...

Roles & ResponsibilitiesJob Description Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies. Work closely with...

Roles & ResponsibilitiesJob Description Working on 6nm and below advanced process project APR and Timing/PI sign-off Take the TOP and PM role for the complicated hierarchical chip (more than 20M inst plus 500+ macros) Take the Block or Block coordinator role for complex blocks Do early prediction for critical APR/Timing/PI issuesJob Requirements ...